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Some hardware designers like to include filtering capacitors into reset lines in order to protect against ESD or other pulses. This increases the raise time of the reset signal. To still reach the required 16 µs reset pulse width, we thus have to increase the reset pulse width via board config.
147 lines
4.1 KiB
Plaintext
147 lines
4.1 KiB
Plaintext
# Copyright (c) 2020 Freie Universitaet Berlin
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#
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# This file is subject to the terms and conditions of the GNU Lesser
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# General Public License v2.1. See the file LICENSE in the top level
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# directory for more details.
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#
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menuconfig KCONFIG_MODULE_AT86RF215
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bool "Configure AT86RF215 driver"
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depends on MODULE_AT86RF215
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help
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Configure the AT86RF215 driver using Kconfig.
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if KCONFIG_MODULE_AT86RF215
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config AT86RF215_USE_CLOCK_OUTPUT
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bool "Enable clock output"
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help
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Enable this to enable the clock output pin of the AT86RF215 chip.
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This way it can be used as a clock source in place of a separate crystal.
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You also have to enable this if you want to measure the clock frequency
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for trimming. After proper trim value is applied this may be disabled
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if not used otherwise.
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By Default it is turned off to save energy.
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config AT86RF215_TRIM_VAL_EN
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bool "Enable crystal oscillator trimming"
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help
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Enable crystal oscillator trimming.
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config AT86RF215_TRIM_VAL
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int "Trim value for the crystal oscillator"
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range 0 15
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default 0
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depends on AT86RF215_TRIM_VAL_EN
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help
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Each increment adds 300nF capacitance between the crystal oscillator pins
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TCXO and XTAL2.Tweak the value until the measured clock output matches
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26 MHz the best.
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For more information Refer Table 6-25 TRIM in Datasheet
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config AT86RF215_RESET_PULSE_WIDTH_US
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int "Width of the reset pulse (µs)"
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range 16 1000
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default 16
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help
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If your board design includes a filtering capacitor on the reset line, this raises
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the rise time of the reset pulse.
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To accommodate for this, select a larger reset pulse width here.
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If unsure, leave this at the default value of 16 µs.
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choice
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prompt "Default Modulation"
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config AT86RF215_DEFAULT_LEGACY_OQPSK
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bool "legacy O-QPSK"
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help
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O-QPSK compatible with IEEE 802.15.4-2003 devices
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config AT86RF215_DEFAULT_MR_OQPSK
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bool "MR-O-QPSK"
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help
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MR-O-QPSK according to IEEE 802.15.4g
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config AT86RF215_DEFAULT_MR_OFDM
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bool "MR-OFDM"
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help
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MR-O-OFDM according to IEEE 802.15.4g
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endchoice
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menu "O-QPSK (802.15.4) configuration"
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depends on AT86RF215_DEFAULT_LEGACY_OQPSK
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config AT86RF215_DEFAULT_OQPSK_RATE
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int "Default (legacy) O-QPSK rate mode"
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range 0 1
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default 0
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help
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The at86rf215 supports proprietary high data rates that are compatible
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with the at86rf2xx parts.
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Set this to 1 to configure the proprietary high-data rate option as default.
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If unsure, leave this at 0.
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endmenu # legacy O-QPSK
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menu "MR-O-QPSK (802.15.4g) configuration"
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depends on AT86RF215_DEFAULT_MR_OQPSK
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config AT86RF215_DEFAULT_MR_OQPSK_RATE
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int "Default MR-O-QPSK rate mode"
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range 0 3
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default 2
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help
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Default Rate Mode of the MR-O-QPSK PHY
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Each increment doubles the PSDU data rate.
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choice
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prompt "Default MR-O-QPSK Chip Rate"
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config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_100
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bool "100 kchip/s"
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config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_200
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bool "200 kchip/s"
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config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_1000
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bool "1000 kchip/s"
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config AT86RF215_DEFAULT_MR_OQPSK_CHIPS_2000
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bool "2000 kchip/s"
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endchoice
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endmenu # MR-O-QPSK
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menu "MR-OFDM (802.15.4g) configuration"
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depends on AT86RF215_DEFAULT_MR_OFDM
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config AT86RF215_DEFAULT_MR_OFDM_OPT
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int "Default MR-OFDM option"
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range 1 4
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default 2
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help
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Default Option of the MR-OFDM PHY
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Each increment halves the PSDU data rate.
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config AT86RF215_DEFAULT_MR_OFDM_MCS
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int "Default MR-OFDM Modulation & Coding Scheme"
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range 0 6
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default 2
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help
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Default Modulation & Coding Scheme of the MR-OFDM PHY.
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Higher schemes correspond to higher data rates and lower range.
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0: BPSK, rate 1⁄2, 4 x frequency repetition
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1: BPSK, rate 1⁄2, 2 x frequency repetition
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2: QPSK, rate 1⁄2, 2 x frequency repetition
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3: QPSK, rate 1⁄2
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4: QPSK, rate 3⁄4
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5: 16-QAM, rate 1⁄2
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6: 16-QAM, rate 3⁄4
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endmenu
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endif # KCONFIG_MODULE_AT86RF215
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