Francisco Molina 8ed8daa493 cpu/cc2538/timer: fix 32 bit timer reload value ... The interval load value was only set to 0xffff regardless of the counter mode used which mad the 32bit timer apparently stop after 0xffff (it would never reach values >0xffff). When a GPTM is configured to one of the 32-bit modes, TAILR appears as a 32-bit register (the upper 16-bits correspond to the contents of the GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of TBILR. Thsi commit set the correct value for TAILR depending on the configured timer mode.		2020-08-12 11:35:42 +02:00
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adc.c	cpu/cc2538/periph: adc_sample() now returns int32_t	2020-01-10 14:13:14 +01:00
gpio.c	cpu/cc2538: GPIO: use bitarithm_test_and_clear()	2020-07-28 12:44:23 +02:00
hwrng.c	cpu/cc2538: adapt and cleanup periph/hwrng	2018-09-03 09:01:42 +02:00
i2c.c	cpu/cc2538: fix I2C compilation error with NDEBUG	2020-01-30 11:57:36 +01:00
Makefile	cpu: make use of Makefile.periph	2017-11-06 12:01:19 +01:00
pm.c	cpu/cc2538/periph/pm: unset OSC_PD when running on 32Mhz	2020-03-21 19:32:24 +01:00
rtt.c	cpu/cc2538: rtt: allow to set alarm and overflow cb independently	2020-08-04 16:22:44 +02:00
spi.c	cpu/cc2538: spi: unify spi_transfer_bytes()	2020-03-09 16:37:07 +01:00
timer.c	cpu/cc2538/timer: fix 32 bit timer reload value	2020-08-12 11:35:42 +02:00
uart.c	cpu/cc2538/uart: uart_write wait for all bytes to be sent	2020-07-22 12:56:12 +02:00