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142c28094e
This is a rewrite of the Kinetis GPIO driver which follows the refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y) macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin. The interrupt pin handling is now implemented as a linked list, this is more memory efficient, but with a minor variation in interrupt latency depending on in what order the pins were initialized at runtime. Because the linked list entries are taken from a shared pool, there is also the possibility of running out of available configuration slots, define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if you need more than 16 pins configured for interrupts in the same application. [1]: https://github.com/RIOT-OS/RIOT/pull/3095
523 lines
18 KiB
C
523 lines
18 KiB
C
/*
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* Copyright (C) 2015 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup board_mulle
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* @{
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*
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* @file
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* @name Peripheral MCU configuration for the Eistec Mulle
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef MULLE_PERIPH_CONF_H_
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#define MULLE_PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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* @name Clock system configuration
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* @{
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*/
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#define KINETIS_CPU_USE_MCG 1
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#define KINETIS_MCG_USE_ERC 1
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#define KINETIS_MCG_USE_PLL 0
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#define KINETIS_MCG_DCO_RANGE (96000000U)
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#define KINETIS_MCG_ERC_OSCILLATOR 0
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#define KINETIS_MCG_ERC_FRDIV 0
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#define KINETIS_MCG_ERC_RANGE 0
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#define KINETIS_MCG_ERC_FREQ (32768U)
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/* Base clocks, used by SystemCoreClockUpdate */
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/** Value of the external crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL_CLK_HZ 8000000u
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/** Value of the external 32k crystal or oscillator clock frequency in Hz */
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#define CPU_XTAL32k_CLK_HZ 32768u
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/** Value of the slow internal oscillator clock frequency in Hz */
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#define CPU_INT_SLOW_CLK_HZ 32768u
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/** Value of the fast internal oscillator clock frequency in Hz */
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#define CPU_INT_FAST_CLK_HZ 4000000u
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/** Default System clock value */
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#define DEFAULT_SYSTEM_CLOCK (CPU_XTAL32k_CLK_HZ * 2929u)
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/** @todo Investigate the side effects of making F_CPU run-time variable */
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#define F_CPU DEFAULT_SYSTEM_CLOCK
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_1_EN 0
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#define TIMER_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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#define TIMER_BASE PIT
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#define TIMER_MAX_VALUE (0xffffffff)
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#define TIMER_CLOCK SystemBusClock
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#define TIMER_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_PIT_SHIFT) = 1)
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/* Timer 0 configuration */
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#define TIMER_0_PRESCALER_CH 0
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#define TIMER_0_COUNTER_CH 1
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#define TIMER_0_ISR isr_pit1
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#define TIMER_0_IRQ_CHAN PIT1_IRQn
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/* Timer 1 configuration */
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#define TIMER_1_PRESCALER_CH 2
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#define TIMER_1_COUNTER_CH 3
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#define TIMER_1_ISR isr_pit3
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#define TIMER_1_IRQ_CHAN PIT3_IRQn
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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#define UART_NUMOF (2U)
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#define UART_0_EN 1
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#define UART_1_EN 1
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#define UART_2_EN 0
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#define UART_3_EN 0
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#define UART_4_EN 0
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#define UART_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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/* UART 0 device configuration */
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#define UART_0_DEV UART1
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#define UART_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 1)
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#define UART_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART1_SHIFT) = 0)
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#define UART_0_CLK (SystemSysClock)
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#define UART_0_IRQ_CHAN UART1_RX_TX_IRQn
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#define UART_0_ISR isr_uart1_status
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/* UART 0 pin configuration */
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#define UART_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
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#define UART_0_PORT PORTC
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#define UART_0_TX_PIN 4
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#define UART_0_RX_PIN 3
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/* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
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* section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
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#define UART_0_AF 3
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#define UART_0_TX_PCR_MUX 3
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#define UART_0_RX_PCR_MUX 3
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/* UART 1 device configuration */
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#define UART_1_DEV UART0
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#define UART_1_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 1)
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#define UART_1_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_UART0_SHIFT) = 0)
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#define UART_1_CLK (SystemSysClock)
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#define UART_1_IRQ_CHAN UART0_RX_TX_IRQn
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#define UART_1_ISR isr_uart0_status
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/* UART 1 pin configuration */
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#define UART_1_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
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#define UART_1_PORT PORTA
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#define UART_1_TX_PIN 14
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#define UART_1_RX_PIN 15
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/* Function number in pin multiplex, see K60 Sub-Family Reference Manual,
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* section 10.3.1 K60 Signal Multiplexing and Pin Assignments */
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#define UART_1_AF 3
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#define UART_1_TX_PCR_MUX 3
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#define UART_1_RX_PCR_MUX 3
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_NUMOF (2U)
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#define ADC_0_EN 1
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#define ADC_1_EN 1
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#define ADC_MAX_CHANNELS 6
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/* ADC 0 configuration */
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#define ADC_0_DEV ADC0
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#define ADC_0_CHANNELS 4
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#define ADC_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 1)
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#define ADC_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_ADC0_SHIFT) = 0)
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#define ADC_0_PORT_CLKEN() /* no PORT pins configured */
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#define ADC_0_MODULE_CLOCK SystemBusClock
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/* ADC 0 channel 0 pin config */
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#define ADC_0_CH0 26 /* Temp sensor channel */
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#define ADC_0_CH0_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_0_CH0_PIN 0
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#define ADC_0_CH0_PIN_AF 0
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/* ADC 0 channel 1 pin config */
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#define ADC_0_CH1 27 /* Band gap channel */
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#define ADC_0_CH1_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_0_CH1_PIN 0
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#define ADC_0_CH1_PIN_AF 0
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/* ADC 0 channel 2 pin config */
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#define ADC_0_CH2 29 /* V_REFSH */
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#define ADC_0_CH2_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_0_CH2_PIN 0
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#define ADC_0_CH2_PIN_AF 0
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/* ADC 0 channel 3 pin config */
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#define ADC_0_CH3 30 /* V_REFSL */
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#define ADC_0_CH3_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_0_CH3_PIN 0
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#define ADC_0_CH3_PIN_AF 0
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/* ADC 0 channel 4 pin config */
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#define ADC_0_CH4 4
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#define ADC_0_CH4_PORT 0
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#define ADC_0_CH4_PIN 0
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#define ADC_0_CH4_PIN_AF 0
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/* ADC 0 channel 5 pin config */
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#define ADC_0_CH5 5
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#define ADC_0_CH5_PORT 0
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#define ADC_0_CH5_PIN 0
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#define ADC_0_CH5_PIN_AF 0
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/* ADC 1 configuration */
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#define ADC_1_DEV ADC1
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#define ADC_1_CHANNELS 2
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#define ADC_1_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 1)
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#define ADC_1_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_ADC1_SHIFT) = 0)
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#define ADC_1_PORT_CLKEN() /* no PORT pins configured */
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#define ADC_1_MODULE_CLOCK SystemBusClock
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/* ADC 1 channel 0 pin config */
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#define ADC_1_CH0 0 /* DADP0, connected externally to Mulle Vbat/2 on PGA1_DP */
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#define ADC_1_CH0_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_1_CH0_PIN 0
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#define ADC_1_CH0_PIN_AF 0
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/* ADC 1 channel 1 pin config */
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#define ADC_1_CH1 19 /* AD19, connected externally to Mulle Vchr/2 on PGA1_DM */
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#define ADC_1_CH1_PORT 0 /* this channel is not part of the pin mux on this CPU */
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#define ADC_1_CH1_PIN 0
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#define ADC_1_CH1_PIN_AF 0
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/* ADC 1 channel 2 pin config */
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#define ADC_1_CH2 12
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#define ADC_1_CH2_PIN 0
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#define ADC_1_CH2_PIN_AF 0
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#define ADC_1_CH2_PORT 0
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/* ADC 1 channel 3 pin config */
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#define ADC_1_CH3 13
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#define ADC_1_CH3_PIN 0
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#define ADC_1_CH3_PIN_AF 0
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#define ADC_1_CH3_PORT 0
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/* ADC 1 channel 4 pin config */
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#define ADC_1_CH4 14
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#define ADC_1_CH4_PIN 0
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#define ADC_1_CH4_PIN_AF 0
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#define ADC_1_CH4_PORT 0
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/* ADC 1 channel 5 pin config */
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#define ADC_1_CH5 15
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#define ADC_1_CH5_PIN 0
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#define ADC_1_CH5_PIN_AF 0
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#define ADC_1_CH5_PORT 0
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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#define PWM_NUMOF (2U)
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#define PWM_0_EN 1
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#define PWM_1_EN 1
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#define PWM_MAX_CHANNELS 8
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#define PWM_MAX_VALUE 0xffff
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/* PWM 0 device configuration */
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#define PWM_0_DEV FTM0
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#define PWM_0_CHANNELS 2
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#define PWM_0_CLK (SystemBusClock)
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#define PWM_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_FTM0_SHIFT) = 1)
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#define PWM_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_FTM0_SHIFT) = 0)
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/* PWM 0 pin configuration */
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#define PWM_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTC_SHIFT) = 1)
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#define PWM_0_PIN_CH0 1
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#define PWM_0_FTMCHAN_CH0 0
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#define PWM_0_PORT_CH0 PORTC
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#define PWM_0_PIN_AF_CH0 4
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#define PWM_0_PIN_CH1 2
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#define PWM_0_FTMCHAN_CH1 1
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#define PWM_0_PORT_CH1 PORTC
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#define PWM_0_PIN_AF_CH1 4
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/* PWM 1 device configuration */
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#define PWM_1_DEV FTM1
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#define PWM_1_CHANNELS 2
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#define PWM_1_CLK (SystemBusClock)
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#define PWM_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_FTM1_SHIFT) = 1)
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#define PWM_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_FTM1_SHIFT) = 0)
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/* PWM 1 pin configuration */
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#define PWM_1_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTA_SHIFT) = 1)
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#define PWM_1_PIN_CH0 12
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#define PWM_1_FTMCHAN_CH0 0
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#define PWM_1_PORT_CH0 PORTA
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#define PWM_1_PIN_AF_CH0 3
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#define PWM_1_PIN_CH1 13
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#define PWM_1_FTMCHAN_CH1 1
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#define PWM_1_PORT_CH1 PORTA
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#define PWM_1_PIN_AF_CH1 3
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF 3
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#define SPI_0_EN 1
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#define SPI_1_EN 1
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#define SPI_2_EN 1
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#define SPI_3_EN 0
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#define SPI_4_EN 0
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#define SPI_5_EN 0
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#define SPI_6_EN 0
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#define SPI_7_EN 0
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#define MULLE_PASTE_PARTS(left, index, right) MULLE_PASTE_PARTS2(left, index, right)
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#define MULLE_PASTE_PARTS2(left, index, right) left##index##right
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/* SPI 0 device config */
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/* SPI_0 (in RIOT) is mapped to SPI0, CTAS=0 in hardware */
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#define SPI_0_INDEX 0
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#define SPI_0_CTAS 0
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#define SPI_0_DEV MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, )
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#define SPI_0_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
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#define SPI_0_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
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#define SPI_0_IRQ MULLE_PASTE_PARTS(SPI, SPI_0_INDEX, _IRQn)
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#define SPI_0_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_0_INDEX, )
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#define SPI_0_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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#define SPI_0_FREQ SystemBusClock
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT PORTD
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#define SPI_0_SCK_PIN 1
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#define SPI_0_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_0_SCK_AF 2
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#define SPI_0_SIN_PORT PORTD
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#define SPI_0_SIN_PIN 3
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#define SPI_0_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_0_SIN_AF 2
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#define SPI_0_SOUT_PORT PORTD
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#define SPI_0_SOUT_PIN 2
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#define SPI_0_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_0_SOUT_AF 2
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#define SPI_0_PCS0_PORT PORTD
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#define SPI_0_PCS0_PIN 0
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#define SPI_0_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_0_PCS0_AF 2
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/* SPI chip select polarity */
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#define SPI_0_PCS0_ACTIVE_LOW 1
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#define SPI_0_PCS1_ACTIVE_LOW 1
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#define SPI_0_PCS2_ACTIVE_LOW 1
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#define SPI_0_PCS3_ACTIVE_LOW 1
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/* SPI 1 device config */
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/* SPI_1 (in RIOT) is mapped to SPI1, CTAS=0 in hardware */
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#define SPI_1_INDEX 1
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#define SPI_1_CTAS 0
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#define SPI_1_DEV MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, )
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#define SPI_1_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 1)
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#define SPI_1_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI1_SHIFT) = 0)
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#define SPI_1_IRQ MULLE_PASTE_PARTS(SPI, SPI_1_INDEX, _IRQn)
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#define SPI_1_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_1_INDEX, )
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#define SPI_1_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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#define SPI_1_FREQ SystemBusClock
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/* SPI 0 pin configuration */
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#define SPI_1_SCK_PORT PORTE
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#define SPI_1_SCK_PIN 2
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#define SPI_1_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
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#define SPI_1_SCK_AF 2
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#define SPI_1_SIN_PORT PORTE
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#define SPI_1_SIN_PIN 3
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#define SPI_1_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
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#define SPI_1_SIN_AF 2
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#define SPI_1_SOUT_PORT PORTE
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#define SPI_1_SOUT_PIN 1
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#define SPI_1_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
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#define SPI_1_SOUT_AF 2
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#define SPI_1_PCS0_PORT PORTE
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#define SPI_1_PCS0_PIN 4
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#define SPI_1_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTE_SHIFT) = 1)
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#define SPI_1_PCS0_AF 2
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/* SPI chip select polarity */
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#define SPI_1_PCS0_ACTIVE_LOW 1
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#define SPI_1_PCS1_ACTIVE_LOW 1
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#define SPI_1_PCS2_ACTIVE_LOW 1
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#define SPI_1_PCS3_ACTIVE_LOW 1
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/* SPI 2 device config */
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/* SPI_2 (in RIOT) is mapped to SPI0, CTAS=1 in hardware */
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#define SPI_2_INDEX 0
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#define SPI_2_CTAS 1
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#define SPI_2_DEV MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, )
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#define SPI_2_CLKEN() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 1)
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#define SPI_2_CLKDIS() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_SPI0_SHIFT) = 0)
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#define SPI_2_IRQ MULLE_PASTE_PARTS(SPI, SPI_2_INDEX, _IRQn)
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/* #define SPI_2_IRQ_HANDLER MULLE_PASTE_PARTS(isr_spi, SPI_2_INDEX, ) */
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#define SPI_2_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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#define SPI_2_FREQ SystemBusClock
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/* SPI 2 pin configuration, must be the same as the other RIOT device using this
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* hardware module */
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#define SPI_2_SCK_PORT PORTD
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#define SPI_2_SCK_PIN 1
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#define SPI_2_SCK_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_2_SCK_AF 2
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#define SPI_2_SIN_PORT PORTD
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#define SPI_2_SIN_PIN 3
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#define SPI_2_SIN_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_2_SIN_AF 2
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#define SPI_2_SOUT_PORT PORTD
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#define SPI_2_SOUT_PIN 2
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#define SPI_2_SOUT_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_2_SOUT_AF 2
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#define SPI_2_PCS0_PORT PORTD
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#define SPI_2_PCS0_PIN 0
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#define SPI_2_PCS0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTD_SHIFT) = 1)
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#define SPI_2_PCS0_AF 2
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/* SPI chip select polarity */
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#define SPI_2_PCS0_ACTIVE_LOW 1
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#define SPI_2_PCS1_ACTIVE_LOW 1
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#define SPI_2_PCS2_ACTIVE_LOW 1
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#define SPI_2_PCS3_ACTIVE_LOW 1
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/**
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* @name SPI delay timing configuration
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* @{ */
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/* These values are necessary for communicating with the AT86RF212B when running
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* the MCU core at high clock frequencies. */
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/* NB: The given values are the reciprocals of the time, in order to compute the
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* scalers using only integer math. */
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#define SPI_0_TCSC_FREQ (5555555) /* It looks silly, but this is correct. 1/180e-9 */
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#define SPI_0_TASC_FREQ (5454545) /* It looks silly, but this is correct. 1/183e-9 */
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#define SPI_0_TDT_FREQ (4000000) /* 1/250e-9 */
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/* SPI_1 timings */
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#define SPI_1_TCSC_FREQ (0)
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#define SPI_1_TASC_FREQ (0)
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#define SPI_1_TDT_FREQ (0)
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/* SPI_2 timings */
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#define SPI_2_TCSC_FREQ (0)
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#define SPI_2_TASC_FREQ (0)
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#define SPI_2_TDT_FREQ (0)
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/** @} */
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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#define I2C_NUMOF (1U)
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#define I2C_CLK SystemBusClock
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#define I2C_0_EN 1
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#define I2C_1_EN 0
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#define I2C_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
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/**
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* @name I2C baud rate configuration
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* @{
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*/
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/* Low (10 kHz): MUL = 4, SCL divider = 2560, total: 10240 */
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#define KINETIS_I2C_F_ICR_LOW (0x3D)
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#define KINETIS_I2C_F_MULT_LOW (2)
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/* Normal (100 kHz): MUL = 2, SCL divider = 240, total: 480 */
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#define KINETIS_I2C_F_ICR_NORMAL (0x1F)
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#define KINETIS_I2C_F_MULT_NORMAL (1)
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/* Fast (400 kHz): MUL = 1, SCL divider = 128, total: 128 */
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#define KINETIS_I2C_F_ICR_FAST (0x17)
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#define KINETIS_I2C_F_MULT_FAST (0)
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/* Fast plus (1000 kHz): MUL = 1, SCL divider = 48, total: 48 */
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#define KINETIS_I2C_F_ICR_FAST_PLUS (0x10)
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#define KINETIS_I2C_F_MULT_FAST_PLUS (0)
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/** @} */
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|
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/* I2C 0 device configuration */
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#define I2C_0_DEV I2C0
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#define I2C_0_CLKEN() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 1)
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#define I2C_0_CLKDIS() (BITBAND_REG32(SIM->SCGC4, SIM_SCGC4_I2C0_SHIFT) = 0)
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#define I2C_0_IRQ I2C0_IRQn
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#define I2C_0_IRQ_HANDLER isr_i2c0
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/* I2C 0 pin configuration */
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#define I2C_0_PORT PORTB
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#define I2C_0_PORT_CLKEN() (BITBAND_REG32(SIM->SCGC5, SIM_SCGC5_PORTB_SHIFT) = 1)
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#define I2C_0_PIN_AF 2
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#define I2C_0_SDA_PIN 1
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#define I2C_0_SCL_PIN 2
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#define I2C_0_PORT_CFG (PORT_PCR_MUX(I2C_0_PIN_AF) | PORT_PCR_ODE_MASK)
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/** @} */
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|
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|
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/**
|
|
* @name GPIO configuration
|
|
* @{
|
|
*/
|
|
#define GPIO_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
|
|
/** @} */
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|
|
/**
|
|
* @name RTC configuration
|
|
* @{
|
|
*/
|
|
/* RIOT RTC implementation uses RTT for underlying timekeeper */
|
|
#define RTC_NUMOF (1U)
|
|
/** @} */
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|
|
/**
|
|
* @name RTT configuration
|
|
* @{
|
|
*/
|
|
#define RTT_NUMOF (1U)
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|
#define RTT_IRQ_PRIO CPU_DEFAULT_IRQ_PRIO
|
|
#define RTT_IRQ RTC_IRQn
|
|
#define RTT_ISR isr_rtc_alarm
|
|
#define RTT_DEV RTC
|
|
#define RTT_UNLOCK() (BITBAND_REG32(SIM->SCGC6, SIM_SCGC6_RTC_SHIFT) = 1)
|
|
#define RTT_MAX_VALUE (0xffffffff)
|
|
#define RTT_FREQUENCY (1) /* in Hz */
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|
|
|
/**
|
|
* RTC module crystal load capacitance configuration bits.
|
|
*/
|
|
/* The crystal on the Mulle is designed for 12.5 pF load capacitance. According
|
|
* to the data sheet, the K60 will have a 5 pF parasitic capacitance on the
|
|
* XTAL32/EXTAL32 connection. The board traces might give some minor parasitic
|
|
* capacitance as well. */
|
|
/* enable 6pF load capacitance, might need adjusting.. */
|
|
#define RTT_LOAD_CAP_BITS (RTC_CR_SC4P_MASK | RTC_CR_SC2P_MASK | RTC_CR_SC1P_MASK)
|
|
/** @} */
|
|
|
|
|
|
/**
|
|
* @name Random Number Generator configuration
|
|
* @{
|
|
*/
|
|
#define RANDOM_NUMOF (1U)
|
|
#define RANDOM_CLKEN() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 1)
|
|
#define RANDOM_CLKDIS() (BITBAND_REG32(SIM->SCGC3, SIM_SCGC3_RNGA_SHIFT) = 0)
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* MULLE_PERIPH_CONF_H_ */
|
|
/** @} */
|