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142c28094e
This is a rewrite of the Kinetis GPIO driver which follows the refactored API in [1]. Pins are specified using the GPIO_PIN(PORT_x, y) macro, e.g. GPIO_PIN(PORT_E, 25) for the PTE25 pin. The interrupt pin handling is now implemented as a linked list, this is more memory efficient, but with a minor variation in interrupt latency depending on in what order the pins were initialized at runtime. Because the linked list entries are taken from a shared pool, there is also the possibility of running out of available configuration slots, define the preprocessor macro GPIO_INT_POOL_SIZE in periph_conf.h if you need more than 16 pins configured for interrupts in the same application. [1]: https://github.com/RIOT-OS/RIOT/pull/3095
163 lines
4.5 KiB
C
163 lines
4.5 KiB
C
/*
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* Copyright (C) 2014 Eistec AB
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @defgroup board_mulle Eistec Mulle
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* @ingroup boards
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* @brief Board specific files for Eistec Mulle IoT boards
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* @{
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*
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* @file
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* @brief Board specific definitions for the Eistec Mulle IoT board
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*
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* @author Joakim Nohlgård <joakim.nohlgard@eistec.se>
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*/
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#ifndef BOARD_H_
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#define BOARD_H_
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#include "cpu.h"
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#include "periph_conf.h"
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#include "mulle-nvram.h"
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/* Use the on board RTC 32kHz clock for LPTMR clocking. */
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#undef LPTIMER_CLKSRC
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/** @brief Clock source for the LPTMR module */
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#define LPTIMER_CLKSRC LPTIMER_CLKSRC_ERCLK32K
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/** Disable hardware watchdog, for debugging purposes, don't use this on production builds. */
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#define DISABLE_WDOG 1
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/**
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* @name Define UART device and baudrate for stdio
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* @{
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*/
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#define STDIO UART_0
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#define STDIO_BAUDRATE (115200U)
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#define STDIO_RX_BUFSIZE (64U)
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/** @} */
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/**
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* @name LEDs configuration
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* @{
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*/
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#define LED_RED_PORT PTC
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#define LED_RED_PIN 15
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#define LED_RED_GPIO GPIO_PIN(PORT_C, LED_RED_PIN)
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#define LED_YELLOW_PORT PTC
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#define LED_YELLOW_PIN 14
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#define LED_YELLOW_GPIO GPIO_PIN(PORT_C, LED_YELLOW_PIN)
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#define LED_GREEN_PORT PTC
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#define LED_GREEN_PIN 13
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#define LED_GREEN_GPIO GPIO_PIN(PORT_C, LED_GREEN_PIN)
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/** @} */
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/**
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* @name Macros for controlling the on-board LEDs.
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* @{
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*/
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#define LED_RED_ON (BITBAND_REG32(LED_RED_PORT->PSOR, LED_RED_PIN) = 1)
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#define LED_RED_OFF (BITBAND_REG32(LED_RED_PORT->PCOR, LED_RED_PIN) = 1)
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#define LED_RED_TOGGLE (BITBAND_REG32(LED_RED_PORT->PTOR, LED_RED_PIN) = 1)
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#define LED_YELLOW_ON (BITBAND_REG32(LED_YELLOW_PORT->PSOR, LED_YELLOW_PIN) = 1)
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#define LED_YELLOW_OFF (BITBAND_REG32(LED_YELLOW_PORT->PCOR, LED_YELLOW_PIN) = 1)
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#define LED_YELLOW_TOGGLE (BITBAND_REG32(LED_YELLOW_PORT->PTOR, LED_YELLOW_PIN) = 1)
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#define LED_GREEN_ON (BITBAND_REG32(LED_GREEN_PORT->PSOR, LED_GREEN_PIN) = 1)
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#define LED_GREEN_OFF (BITBAND_REG32(LED_GREEN_PORT->PCOR, LED_GREEN_PIN) = 1)
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#define LED_GREEN_TOGGLE (BITBAND_REG32(LED_GREEN_PORT->PTOR, LED_GREEN_PIN) = 1)
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/** @} */
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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/**
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* @name Define the interface to the AT86RF212B radio
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* @{
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*/
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#define AT86RF231_SPI SPI_0
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#define AT86RF231_CS GPIO_PIN(PORT_D, 4)
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#define AT86RF231_INT GPIO_PIN(PORT_B, 9)
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/** @todo work around missing RESET pin on Mulle v0.6x */
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#define AT86RF231_RESET GPIO_PIN(PORT_C, 12)
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#define AT86RF231_SLEEP GPIO_PIN(PORT_E, 6)
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#define AT86RF231_SPI_CLK SPI_SPEED_5MHZ
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/** @} */
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/**
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* @name LIS3DH configuration
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* @{
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*/
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#define LIS3DH_INT1 GPIO_PIN(PORT_C, 18)
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#define LIS3DH_INT2 GPIO_PIN(PORT_C, 17)
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#define LIS3DH_CS GPIO_PIN(PORT_D, 0)
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#define LIS3DH_SPI SPI_2
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/** @} */
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/**
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* @name Mulle power control configuration
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*/
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/** @{ */
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#define MULLE_POWER_AVDD GPIO_PIN(PORT_B, 17) /**< AVDD enable pin */
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#define MULLE_POWER_VPERIPH GPIO_PIN(PORT_D, 7) /**< VPERIPH enable pin */
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#define MULLE_POWER_VSEC GPIO_PIN(PORT_B, 16) /**< VSEC enable pin */
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/** @} */
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/**
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* @name Mulle NVRAM hardware configuration
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*/
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/** @{ */
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/** FRAM SPI bus, SPI_2 in RIOT is mapped to hardware bus SPI0, see periph_conf.h */
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#define MULLE_NVRAM_SPI_DEV SPI_2
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#define MULLE_NVRAM_SPI_CS GPIO_PIN(PORT_D, 6) /**< FRAM CS pin */
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#define MULLE_NVRAM_CAPACITY 512 /**< FRAM size, in bytes */
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#define MULLE_NVRAM_SPI_ADDRESS_COUNT 1 /**< FRAM addressing size, in bytes */
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/** @} */
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/**
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* @name K60 clock dividers
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*/
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/** @{ */
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/**
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* System clock divider setting, the actual hardware register value, see reference manual for details.
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*/
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#define CONFIG_CLOCK_K60_SYS_DIV 0x00
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/**
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* Bus clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_BUS_DIV 0x01
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/**
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* Flexbus clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_FB_DIV 0x01
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/**
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* Flash clock divider setting, the actual hardware register value, see reference manual for details
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*/
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#define CONFIG_CLOCK_K60_FLASH_DIV 0x03
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/** @} */
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#endif /* BOARD_H_ */
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/** @} */
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