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https://github.com/RIOT-OS/RIOT.git
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32b1546053
Split the SDK defintions sdkconfig.h into a part that is common for all ESP32x SoCs and a part that is specific for ESP32.
263 lines
8.3 KiB
C
263 lines
8.3 KiB
C
/*
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* Copyright (C) 2022 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_esp32
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* @{
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*
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* @file
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* @brief SDK configuration used by the ESP-IDF for ESP32
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*
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* The SDK configuration can be partially overridden by application-specific
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* board configuration.
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*
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef SDKCONFIG_ESP32_H
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#define SDKCONFIG_ESP32_H
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#ifndef DOXYGEN
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock configuration
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* @{
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*/
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/* Mapping of Kconfig defines to the respective enumeration values */
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#if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_2
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 2
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_5
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 5
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_10
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 10
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_20
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 20
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_40
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 40
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_80
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_160
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 160
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#elif CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ_240
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 240
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#endif
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/**
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* @brief Defines the CPU frequency [values = 2, 40, 80, 160 and 240]
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*/
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#ifndef CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ
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#define CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ 80
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#endif
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/**
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* @brief Mapping configured ESP32 default clock to CLOCK_CORECLOCK define
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*/
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#define CLOCK_CORECLOCK (1000000UL * CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ)
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/** @} */
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/**
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* Default console configuration
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*
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* STDIO_UART_BAUDRATE is used as CONFIG_CONSOLE_UART_BAUDRATE and
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* can be overridden by an application specific configuration.
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*/
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#define CONFIG_CONSOLE_UART_NUM 0
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#define CONFIG_ESP_CONSOLE_UART_NUM CONFIG_CONSOLE_UART_NUM
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#ifndef CONFIG_CONSOLE_UART_BAUDRATE
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#define CONFIG_CONSOLE_UART_BAUDRATE STDIO_UART_BAUDRATE
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#endif
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/**
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* Log output configuration (DO NOT CHANGE)
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*/
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#ifndef CONFIG_LOG_DEFAULT_LEVEL
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#define CONFIG_LOG_DEFAULT_LEVEL LOG_LEVEL
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#endif
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#define CONFIG_LOG_MAXIMUM_LEVEL LOG_LEVEL
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/**
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* ESP32 specific configuration
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*
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* Main clock crystal frequency (MHz). Zero means to auto-configure.
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* This is configured at the board level, defaulting to 40.
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*/
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#ifndef CONFIG_ESP32_XTAL_FREQ
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#define CONFIG_ESP32_XTAL_FREQ 0
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#endif
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#ifdef MODULE_ESP_RTC_TIMER_32K
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#define CONFIG_ESP32_RTC_CLK_SRC_EXT_CRYS 1
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#endif
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#define CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES 100
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#define CONFIG_ESP32_RTC_CLK_CAL_CYCLES (8 * 1024)
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/**
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* System specific configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_NEWLIB_NANO
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#define CONFIG_NEWLIB_NANO_FORMAT 1
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#endif
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#define CONFIG_TRACEMEM_RESERVE_DRAM 0
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#define CONFIG_ULP_COPROC_RESERVE_MEM 0
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#define CONFIG_ESP_SYSTEM_CHECK_INT_LEVEL_4 1
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#define CONFIG_ESP_SYSTEM_EVENT_QUEUE_SIZE 32
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#define CONFIG_ESP_SYSTEM_EVENT_TASK_STACK_SIZE 2560
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#define CONFIG_NUMBER_OF_UNIVERSAL_MAC_ADDRESS 4
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#define CONFIG_ESP32_DEEP_SLEEP_WAKEUP_DELAY 2000
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#define CONFIG_ESP_TIMER_INTERRUPT_LEVEL 1
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#define CONFIG_ESP_TIMER_TASK_STACK_SIZE 3584
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#define CONFIG_ESP_TIMER_IMPL_FRC2 1
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#define CONFIG_ESP_TIME_FUNCS_USE_ESP_TIMER 1
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#define CONFIG_APP_BUILD_USE_FLASH_SECTIONS 1
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#define CONFIG_EFUSE_MAX_BLK_LEN 192
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#define CONFIG_PARTITION_TABLE_OFFSET 0x8000
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/**
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* Bluetooth configuration (DO NOT CHANGE)
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*/
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#define CONFIG_BT_ENABLED 0
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#define CONFIG_BT_RESERVE_DRAM 0
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/**
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* SPI RAM configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_SPI_RAM
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#define CONFIG_SOC_SPIRAM_SUPPORTED 1
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#define CONFIG_ESP32_SPIRAM_SUPPORT 1
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#define CONFIG_D0WD_PSRAM_CLK_IO 17
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#define CONFIG_D0WD_PSRAM_CS_IO 16
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#define CONFIG_D2WD_PSRAM_CLK_IO 9
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#define CONFIG_D2WD_PSRAM_CS_IO 10
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#define CONFIG_PICO_PSRAM_CS_IO 10
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#define CONFIG_SPIRAM_SUPPORT CONFIG_ESP32_SPIRAM_SUPPORT
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#define CONFIG_SPIRAM 1
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#define CONFIG_SPIRAM_BANKSWITCH_ENABLE 1
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#define CONFIG_SPIRAM_BANKSWITCH_RESERVE 8
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#define CONFIG_SPIRAM_BOOT_INIT 1
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#define CONFIG_SPIRAM_CACHE_WORKAROUND 1
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#define CONFIG_SPIRAM_CACHE_WORKAROUND_STRATEGY_MEMW 1
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#define CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL 16384
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#define CONFIG_SPIRAM_MALLOC_RESERVE_INTERNAL 32768
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#define CONFIG_SPIRAM_MEMTEST 1
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#define CONFIG_SPIRAM_SIZE -1
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#define CONFIG_SPIRAM_SPEED_40M 1
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#define CONFIG_SPIRAM_SPIWP_SD3_PIN 7
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#define CONFIG_SPIRAM_TYPE_AUTO 1
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#define CONFIG_SPIRAM_USE_MALLOC 0 /* using malloc requires QStaticQueue */
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#endif
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/**
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* SPI Flash driver configuration (DO NOT CHANGE)
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*/
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#define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1
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#define CONFIG_SPI_FLASH_USE_LEGACY_IMPL 1
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/**
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* Ethernet driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_ETH
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#define CONFIG_ETH_ENABLED 1
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#endif
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#define CONFIG_ETH_USE_ESP32_EMAC 1
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#define CONFIG_ETH_PHY_INTERFACE_RMII 1
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#define CONFIG_ETH_RMII_CLK_INPUT 1
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#define CONFIG_ETH_RMII_CLK_IN_GPIO 0
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#define CONFIG_ETH_DMA_BUFFER_SIZE 512
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#define CONFIG_ETH_DMA_RX_BUFFER_NUM 10
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#define CONFIG_ETH_DMA_TX_BUFFER_NUM 10
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/**
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* Serial flasher config (DO NOT CHANGE)
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*/
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#define CONFIG_ESPTOOLPY_FLASHFREQ_40M 1
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#if defined(FLASH_MODE_QIO)
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#define CONFIG_FLASHMODE_QIO 1
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#define CONFIG_ESPTOOLPY_FLASHMODE_QIO 1
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#elif defined(FLASH_MODE_QOUT)
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#define CONFIG_FLASHMODE_QOUT 1
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#define CONFIG_ESPTOOLPY_FLASHMODE_QOUT 1
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#elif defined(FLASH_MODE_DIO)
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#define CONFIG_FLASHMODE_DIO 1
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#define CONFIG_ESPTOOLPY_FLASHMODE_DIO 1
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#elif defined(FLASH_MODE_DOUT)
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#define CONFIG_FLASHMODE_DOUT 1
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#define CONFIG_ESPTOOLPY_FLASHMODE_DOUT 1
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#else
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#error "Unknown flash mode selected."
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#endif
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/**
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* Wi-Fi driver configuration (DO NOT CHANGE)
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*/
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#ifdef MODULE_ESP_WIFI_ANY
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#define CONFIG_ESP32_WIFI_ENABLED 1
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#endif
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#if defined(MODULE_ESP_WIFI_AP) || defined(MODULE_ESP_NOW)
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#define CONFIG_ESP_WIFI_SOFTAP_SUPPORT 1
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#endif
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#define CONFIG_ESP32_WIFI_STATIC_RX_BUFFER_NUM 10
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#define CONFIG_ESP32_WIFI_DYNAMIC_RX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER 1
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#define CONFIG_ESP32_WIFI_TX_BUFFER_TYPE 1
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#define CONFIG_ESP32_WIFI_DYNAMIC_TX_BUFFER_NUM 32
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#define CONFIG_ESP32_WIFI_CACHE_TX_BUFFER_NUM 32 /* required when CONFIG_SPIRAM_USE_MALLOC=0 */
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#define CONFIG_ESP32_WIFI_AMPDU_TX_ENABLED 1
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#define CONFIG_ESP32_WIFI_TX_BA_WIN 6
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#define CONFIG_ESP32_WIFI_AMPDU_RX_ENABLED 1
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#define CONFIG_ESP32_WIFI_RX_BA_WIN 6
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#if MODULE_ESP_IDF_NVS_ENABLED
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#define CONFIG_ESP32_WIFI_NVS_ENABLED 1
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#endif
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#define CONFIG_ESP32_WIFI_TASK_PINNED_TO_CORE_0 1
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#define CONFIG_ESP32_WIFI_SOFTAP_BEACON_MAX_LEN 752
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#define CONFIG_ESP32_WIFI_MGMT_SBUF_NUM 32
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#define CONFIG_ESP32_WIFI_IRAM_OPT 1
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#define CONFIG_ESP32_WIFI_RX_IRAM_OPT 1
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#define CONFIG_ESP32_WIFI_ENABLE_WPA3_SAE 1
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/**
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* PHY configuration
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*/
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#if MODULE_ESP_IDF_NVS_ENABLED
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#define CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE 1
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#endif
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#define CONFIG_ESP_PHY_INIT_DATA_IN_PARTITION 0
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#define CONFIG_ESP_PHY_MAX_TX_POWER 20
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#define CONFIG_ESP_PHY_MAX_WIFI_TX_POWER 20
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#define CONFIG_ESP_PHY_REDUCE_TX_POWER 1
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#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
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#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
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#define CONFIG_ESP32_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
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#define CONFIG_REDUCE_PHY_TX_POWER CONFIG_ESP_PHY_REDUCE_TX_POWER
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/**
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* EMAC driver configuration (DO NOT CHANGE)
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*/
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#define CONFIG_EMAC_L2_TO_L3_RX_BUF_MODE 1
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#ifdef __cplusplus
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}
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#endif
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#endif /* DOXYGEN */
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#endif /* SDKCONFIG_ESP32_H */
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/** @} */
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