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ef4b58f4f0
The QN908x CPU has several timer modules: one RTC (Real-Time Clock) that can count from the 32kHz internal clock or 32.768 kHz external clock, four CTIMER that use the APB clock and have four channels each and one SCT timer with up to 10 channels running on the AHB clock. This patch implements a timer driver for the CTIMER blocks only, which is enough to make the xtimer module work. Future patches should improve on this module to support using the RTC CNT2 32-bit free-running counter unit and/or the SCT timer.
175 lines
4.2 KiB
C
175 lines
4.2 KiB
C
/*
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* Copyright (C) 2020 iosabi
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_qn908x
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* @ingroup drivers_periph_timer
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*
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* @{
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*
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* @file
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* @brief Low-level timer driver implementation
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*
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* This driver leverages the Freescale/NXP implementation distributed with the
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* SDK.
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*
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* @author iosabi <iosabi@protonmail.com>
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*
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* @}
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*/
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#include <stdlib.h>
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#include "cpu.h"
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#include "board.h"
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#include "periph_conf.h"
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#include "periph/timer.h"
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#include "vendor/drivers/fsl_clock.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @brief Interrupt context information for configured timers.
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*/
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static timer_isr_ctx_t isr_ctx[FSL_FEATURE_SOC_CTIMER_COUNT];
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/**
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* @brief CTIMER peripheral base pointers.
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*/
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static CTIMER_Type* const ctimers[FSL_FEATURE_SOC_CTIMER_COUNT] =
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CTIMER_BASE_PTRS;
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/**
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* @brief CTIMER IRQ numbers.
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*/
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static IRQn_Type const ctimers_irqn[FSL_FEATURE_SOC_CTIMER_COUNT] =
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CTIMER_IRQS;
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/**
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* @brief CTIMER Clocks.
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*/
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static const clock_ip_name_t ctimers_clocks[FSL_FEATURE_SOC_CTIMER_COUNT] =
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CTIMER_CLOCKS;
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/**
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* @brief Check the board config to make sure we do not exceed max number of
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* timers
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*/
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#if TIMER_NUMOF > FSL_FEATURE_SOC_CTIMER_COUNT
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#error "ERROR in board timer configuration: too many timers defined"
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#endif
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int timer_init(tim_t tim, unsigned long freq, timer_cb_t cb, void *arg)
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{
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DEBUG("timer_init(%u, %lu)\n", tim, freq);
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if (tim >= TIMER_NUMOF) {
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return -1;
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}
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isr_ctx[tim].cb = cb;
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isr_ctx[tim].arg = arg;
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CLOCK_EnableClock(ctimers_clocks[tim]);
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CTIMER_Type *dev = ctimers[tim];
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/* CTIMER blocks are driven from the APB clock. */
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uint32_t core_freq = CLOCK_GetFreq(kCLOCK_ApbClk);
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uint32_t prescale = (core_freq + freq / 2) / freq - 1;
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if (prescale == (uint32_t)(-1)) {
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DEBUG("timer_init: Frequency %lu is too fast for core_freq=%lu",
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freq, core_freq);
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return -1;
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}
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dev->CTCR = CTIMER_CTCR_CTMODE(0); /* timer mode */
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dev->PR = CTIMER_PR_PRVAL(prescale);
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/* Enable timer interrupts in the NVIC. */
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NVIC_EnableIRQ(ctimers_irqn[tim]);
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/* Timer should be started after init. */
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dev->TCR |= CTIMER_TCR_CEN_MASK;
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return 0;
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}
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int timer_set_absolute(tim_t tim, int channel, unsigned int value)
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{
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DEBUG("timer_set_absolute(%u, %u, %u)\n", tim, channel, value);
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if ((tim >= TIMER_NUMOF) || (channel >= TIMER_CHANNELS)) {
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return -1;
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}
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CTIMER_Type* const dev = ctimers[tim];
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dev->MR[channel] = value;
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dev->MCR |= (CTIMER_MCR_MR0I_MASK << (channel * 3));
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return 0;
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}
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int timer_clear(tim_t tim, int channel)
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{
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DEBUG("timer_clear(%u, %d)\n", tim, channel);
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if ((tim >= TIMER_NUMOF) || (channel >= TIMER_CHANNELS)) {
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return -1;
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}
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CTIMER_Type* const dev = ctimers[tim];
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dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (channel * 3));
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return 0;
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}
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unsigned int timer_read(tim_t tim)
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{
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DEBUG("timer_read(%u) --> %" PRIu32 "\n", tim, ctimers[tim]->TC);
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return ctimers[tim]->TC;
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}
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void timer_start(tim_t tim)
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{
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DEBUG("timer_start(%u)\n", tim);
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ctimers[tim]->TCR |= CTIMER_TCR_CEN_MASK;
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}
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void timer_stop(tim_t tim)
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{
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DEBUG("timer_stop(%u)\n", tim);
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ctimers[tim]->TCR &= ~CTIMER_TCR_CEN_MASK;
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}
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static inline void isr_ctimer_n(CTIMER_Type *dev, uint32_t ctimer_num)
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{
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DEBUG("isr_ctimer_%" PRIu32 " flags=0x%" PRIx32 "\n",
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ctimer_num, dev->IR);
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for (uint32_t i = 0; i < TIMER_CHANNELS; i++) {
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if (dev->IR & (1u << i)) {
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/* Note: setting the bit to 1 in the flag register will clear the
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* bit. */
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dev->IR = 1u << i;
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dev->MCR &= ~(CTIMER_MCR_MR0I_MASK << (i * 3));
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isr_ctx[ctimer_num].cb(isr_ctx[ctimer_num].arg, 0);
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}
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}
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cortexm_isr_end();
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}
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#ifdef CTIMER0
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void isr_ctimer0(void) { isr_ctimer_n(CTIMER0, 0); }
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#endif /* CTIMER0 */
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#ifdef CTIMER1
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void isr_ctimer1(void) { isr_ctimer_n(CTIMER1, 1); }
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#endif /* CTIMER1 */
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#ifdef CTIMER2
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void isr_ctimer2(void) { isr_ctimer_n(CTIMER2, 2); }
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#endif /* CTIMER2 */
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#ifdef CTIMER3
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void isr_ctimer3(void) { isr_ctimer_n(CTIMER3, 3); }
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#endif /* CTIMER3 */
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