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Kaspar Schleiser
ef099f9d46
They might not be necessary, but GCC warns if they're absent. Thus let's pay the one or two extra instructions for silencing the warnings.
97 lines
2.2 KiB
C
97 lines
2.2 KiB
C
/*
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* Copyright (C) 2014 Freie Universität Berlin
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* 2020 Otto-von-Guericke-Universität Magdeburg
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430_common
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* @{
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*
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* @file
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* @brief ISR related functions
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*
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* @author Kaspar Schleiser <kaspar@schleiser.de>
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* @author Oliver Hahm <oliver.hahm@inria.fr>
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* @author Marian Buschsieweke <marian.buschsieweke@ovgu.de>
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*
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*/
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#ifndef IRQ_ARCH_H
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#define IRQ_ARCH_H
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#include "irq.h"
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*
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* gcc warns for missing NOPs before/after interrupt enable/disable.
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* so I added the NOP instructions, even though they might not be necessary
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* due to following AND. // Kaspar
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*/
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extern volatile int __irq_is_in;
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__attribute__((always_inline)) static inline unsigned int irq_disable(void)
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{
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unsigned int state;
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__asm__ volatile(
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"mov.w r2, %[state]" "\n\t"
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"bic %[gie], r2" "\n\t"
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"nop" "\n\t"
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"and %[gie], %[state]" "\n\t"
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: [state] "=r"(state)
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: [gie] "i"(GIE)
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: "memory"
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);
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return state;
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}
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__attribute__((always_inline)) static inline unsigned int irq_enable(void)
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{
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unsigned int state;
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__asm__ volatile(
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"mov.w r2, %[state]" "\n\t"
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"nop" "\n\t"
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"bis %[gie], r2" "\n\t"
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"nop" "\n\t"
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"and %[gie], %[state]" "\n\t"
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: [state] "=r"(state)
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: [gie] "i"(GIE)
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: "memory"
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);
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return state;
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}
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__attribute__((always_inline)) static inline void irq_restore(unsigned int state)
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{
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__asm__ volatile(
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"bis %[state], r2" "\n\t"
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"nop" "\n\t"
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: /* no outputs */
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: [state] "r"(state)
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: "memory"
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);
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}
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__attribute__((always_inline)) static inline int irq_is_in(void)
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{
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return __irq_is_in;
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}
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#ifdef __cplusplus
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}
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#endif
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/** @} */
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#endif /* IRQ_ARCH_H */
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