mirror of
https://github.com/RIOT-OS/RIOT.git
synced 2024-12-29 04:50:03 +01:00
09d1dcf6b3
- Created new `bluepill-128kib` as 128KiB version of the `bluepill` - Created new `blackpill-128kib` as 128KiB version of the `blackpill` - Updated `openocd.cfg` to allow flashing 128KiB of ROM
263 lines
6.9 KiB
C
263 lines
6.9 KiB
C
/*
|
|
* Copyright (C) 2015 TriaGnoSys GmbH
|
|
* 2017 Alexander Kurth, Sören Tempel, Tristan Bruns
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU Lesser
|
|
* General Public License v2.1. See the file LICENSE in the top level
|
|
* directory for more details.
|
|
*/
|
|
|
|
/**
|
|
* @ingroup boards_common_blxxxpill
|
|
* @{
|
|
*
|
|
* @file
|
|
* @brief Peripheral MCU configuration for the bluepill/blackpill boards
|
|
*
|
|
* @author Víctor Ariño <victor.arino@triagnosys.com>
|
|
* @author Sören Tempel <tempel@uni-bremen.de>
|
|
* @author Tristan Bruns <tbruns@uni-bremen.de>
|
|
* @author Alexander Kurth <kurth1@uni-bremen.de>
|
|
*
|
|
*/
|
|
|
|
#ifndef PERIPH_CONF_H
|
|
#define PERIPH_CONF_H
|
|
|
|
#include "periph_cpu.h"
|
|
|
|
#ifdef __cplusplus
|
|
extern "C" {
|
|
#endif
|
|
|
|
/**
|
|
* @name Clock settings
|
|
*
|
|
* @note This is auto-generated from
|
|
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
|
|
* @{
|
|
*/
|
|
/* give the target core clock (HCLK) frequency [in Hz],
|
|
* maximum: 72MHz */
|
|
#define CLOCK_CORECLOCK (72000000U)
|
|
/* 0: no external high speed crystal available
|
|
* else: actual crystal frequency [in Hz] */
|
|
#define CLOCK_HSE (8000000U)
|
|
/* 0: no external low speed crystal available,
|
|
* 1: external crystal available (always 32.768kHz) */
|
|
#define CLOCK_LSE (1U)
|
|
/* peripheral clock setup */
|
|
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
|
|
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
|
|
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2 /* max 36MHz */
|
|
#define CLOCK_APB1 (CLOCK_CORECLOCK / 2)
|
|
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* max 72MHz */
|
|
#define CLOCK_APB2 (CLOCK_CORECLOCK / 1)
|
|
|
|
/* PLL factors */
|
|
#define CLOCK_PLL_PREDIV (1)
|
|
#define CLOCK_PLL_MUL (9)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name ADC configuration
|
|
* @{
|
|
*/
|
|
#define ADC_CONFIG { \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 0), .chan = 0 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 1), .chan = 1 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 2), .chan = 2 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 3), .chan = 3 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 4), .chan = 4 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 5), .chan = 5 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 6), .chan = 6 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_A, 7), .chan = 7 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_B, 0), .chan = 8 }, \
|
|
{ .dev = 0, .pin = GPIO_PIN(PORT_B, 1), .chan = 9 }, \
|
|
}
|
|
|
|
#define ADC_NUMOF 10
|
|
/** @} */
|
|
|
|
/**
|
|
* @name Timer configuration
|
|
* @{
|
|
*/
|
|
static const timer_conf_t timer_config[] = {
|
|
{
|
|
.dev = TIM2,
|
|
.max = 0x0000ffff,
|
|
.rcc_mask = RCC_APB1ENR_TIM2EN,
|
|
.bus = APB1,
|
|
.irqn = TIM2_IRQn
|
|
},
|
|
{
|
|
.dev = TIM3,
|
|
.max = 0x0000ffff,
|
|
.rcc_mask = RCC_APB1ENR_TIM3EN,
|
|
.bus = APB1,
|
|
.irqn = TIM3_IRQn
|
|
},
|
|
{
|
|
.dev = TIM4,
|
|
.max = 0x0000ffff,
|
|
.rcc_mask = RCC_APB1ENR_TIM4EN,
|
|
.bus = APB1,
|
|
.irqn = TIM4_IRQn
|
|
}
|
|
};
|
|
|
|
#define TIMER_0_ISR isr_tim2
|
|
#define TIMER_1_ISR isr_tim3
|
|
#define TIMER_2_ISR isr_tim4
|
|
|
|
#define TIMER_NUMOF ARRAY_SIZE(timer_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name UART configuration
|
|
* @{
|
|
*/
|
|
static const uart_conf_t uart_config[] = {
|
|
{
|
|
.dev = USART1,
|
|
.rcc_mask = RCC_APB2ENR_USART1EN,
|
|
.rx_pin = GPIO_PIN(PORT_A, 10),
|
|
.tx_pin = GPIO_PIN(PORT_A, 9),
|
|
.bus = APB2,
|
|
.irqn = USART1_IRQn
|
|
},
|
|
{
|
|
.dev = USART2,
|
|
.rcc_mask = RCC_APB1ENR_USART2EN,
|
|
.rx_pin = GPIO_PIN(PORT_A, 3),
|
|
.tx_pin = GPIO_PIN(PORT_A, 2),
|
|
.bus = APB1,
|
|
.irqn = USART2_IRQn
|
|
},
|
|
{
|
|
.dev = USART3,
|
|
.rcc_mask = RCC_APB1ENR_USART3EN,
|
|
.rx_pin = GPIO_PIN(PORT_B, 11),
|
|
.tx_pin = GPIO_PIN(PORT_B, 10),
|
|
.bus = APB1,
|
|
.irqn = USART3_IRQn
|
|
}
|
|
};
|
|
|
|
#define UART_0_ISR (isr_usart1)
|
|
#define UART_1_ISR (isr_usart2)
|
|
#define UART_2_ISR (isr_usart3)
|
|
|
|
#define UART_NUMOF ARRAY_SIZE(uart_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name I2C configuration
|
|
* @note This board may require external pullup resistors for i2c operation.
|
|
* @{
|
|
*/
|
|
static const i2c_conf_t i2c_config[] = {
|
|
{
|
|
.dev = I2C1,
|
|
.speed = I2C_SPEED_NORMAL,
|
|
.scl_pin = GPIO_PIN(PORT_B, 6),
|
|
.sda_pin = GPIO_PIN(PORT_B, 7),
|
|
.bus = APB1,
|
|
.rcc_mask = RCC_APB1ENR_I2C1EN,
|
|
.clk = CLOCK_APB1,
|
|
.irqn = I2C1_EV_IRQn
|
|
},
|
|
{
|
|
.dev = I2C2,
|
|
.speed = I2C_SPEED_NORMAL,
|
|
.scl_pin = GPIO_PIN(PORT_B, 10),
|
|
.sda_pin = GPIO_PIN(PORT_B, 11),
|
|
.bus = APB1,
|
|
.rcc_mask = RCC_APB1ENR_I2C2EN,
|
|
.clk = CLOCK_APB1,
|
|
.irqn = I2C2_EV_IRQn
|
|
}
|
|
};
|
|
|
|
#define I2C_0_ISR isr_i2c1_ev
|
|
#define I2C_1_ISR isr_i2c2_ev
|
|
|
|
#define I2C_NUMOF ARRAY_SIZE(i2c_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name PWM configuration
|
|
* @{
|
|
*/
|
|
static const pwm_conf_t pwm_config[] = {
|
|
{
|
|
.dev = TIM1,
|
|
.rcc_mask = RCC_APB2ENR_TIM1EN,
|
|
.chan = { { .pin = GPIO_PIN(PORT_A, 8), .cc_chan = 0 },
|
|
{ .pin = GPIO_PIN(PORT_A, 9), .cc_chan = 1 },
|
|
{ .pin = GPIO_PIN(PORT_A, 10), .cc_chan = 2 },
|
|
{ .pin = GPIO_PIN(PORT_A, 11), .cc_chan = 3 } },
|
|
.af = GPIO_AF_OUT_PP,
|
|
.bus = APB2
|
|
}
|
|
};
|
|
|
|
#define PWM_NUMOF ARRAY_SIZE(pwm_config)
|
|
/** @} */
|
|
|
|
/**
|
|
* @name SPI configuration
|
|
*
|
|
* @note The spi_divtable is auto-generated from
|
|
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
|
|
* @{
|
|
*/
|
|
static const uint8_t spi_divtable[2][5] = {
|
|
{ /* for APB1 @ 36000000Hz */
|
|
7, /* -> 140625Hz */
|
|
6, /* -> 281250Hz */
|
|
4, /* -> 1125000Hz */
|
|
2, /* -> 4500000Hz */
|
|
1 /* -> 9000000Hz */
|
|
},
|
|
{ /* for APB2 @ 72000000Hz */
|
|
7, /* -> 281250Hz */
|
|
7, /* -> 281250Hz */
|
|
5, /* -> 1125000Hz */
|
|
3, /* -> 4500000Hz */
|
|
2 /* -> 9000000Hz */
|
|
}
|
|
};
|
|
|
|
static const spi_conf_t spi_config[] = {
|
|
{
|
|
.dev = SPI1,
|
|
.mosi_pin = GPIO_PIN(PORT_A, 7),
|
|
.miso_pin = GPIO_PIN(PORT_A, 6),
|
|
.sclk_pin = GPIO_PIN(PORT_A, 5),
|
|
.cs_pin = GPIO_PIN(PORT_A, 4),
|
|
.rccmask = RCC_APB2ENR_SPI1EN,
|
|
.apbbus = APB2
|
|
},
|
|
{
|
|
.dev = SPI2,
|
|
.mosi_pin = GPIO_PIN(PORT_B, 15),
|
|
.miso_pin = GPIO_PIN(PORT_B, 14),
|
|
.sclk_pin = GPIO_PIN(PORT_B, 13),
|
|
.cs_pin = GPIO_PIN(PORT_B, 12),
|
|
.rccmask = RCC_APB1ENR_SPI2EN,
|
|
.apbbus = APB1
|
|
}
|
|
};
|
|
|
|
#define SPI_NUMOF ARRAY_SIZE(spi_config)
|
|
/** @} */
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* PERIPH_CONF_H */
|
|
/** @} */
|