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241087fd76
specific support for the pic32mz2046efg100 is added along with code common to all pic32 devices and all pic32mz devices.
53 lines
1.3 KiB
C
53 lines
1.3 KiB
C
/*
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* Copyright(C) 2016,2017, Imagination Technologies Limited and/or its
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* affiliated group companies.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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#include <assert.h>
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#include "board.h"
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#include "../mips32r2_common/include/eic_irq.h"
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void eic_irq_configure(int irq_num)
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{
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/* Only timer interrupt supported currently */
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assert(irq_num == EIC_IRQ_TIMER);
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/* Enable IRQ0 CPU Timer Interrupt */
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IEC0SET = _IEC0_CTIE_MASK;
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/* Set IRQ 0 to priority 1.0 */
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IPC0SET = 1 << _IPC0_CTIP_POSITION | 0 << _IPC0_CTIS_POSITION;
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}
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void eic_irq_enable(int irq_num)
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{
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/* Only timer interrupt supported currently */
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assert(irq_num == EIC_IRQ_TIMER);
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/* Enable IRQ0 CPU Timer Interrupt */
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IEC0SET = _IEC0_CTIE_MASK;
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}
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void eic_irq_disable(int irq_num)
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{
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/* Only timer interrupt supported currently */
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assert(irq_num == EIC_IRQ_TIMER);
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/* Disable IRQ0 CPU Timer Interrupt */
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IEC0CLR = _IEC0_CTIE_MASK;
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}
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void eic_irq_ack(int irq_num)
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{
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/* Only timer interrupt supported currently */
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assert(irq_num == EIC_IRQ_TIMER);
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/* Ack the timer interrupt */
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IFS0CLR =_IFS0_CTIF_MASK;
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}
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