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391164a788
Prevent CPU from using cortexm_init() when softdevice is used for NRF52 devices as the softdevice already do some obscur inits Also ensure the softdevice pkg will be used by hacking Makefile due to RIOT's build system limitations (will be fix later with the new build system)
131 lines
3.2 KiB
C
131 lines
3.2 KiB
C
/*
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* Copyright (C) 2015 Jan Wagner <mail@jwagner.eu>
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* 2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_nrf52
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* @{
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*
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* @file
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* @brief Implementation of the CPU initialization
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Jan Wagner <mail@jwagner.eu>
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*
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* @}
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*/
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#define DONT_OVERRIDE_NVIC
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#include "cpu.h"
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#include "nrf_clock.h"
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#include "periph_conf.h"
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#include "periph/init.h"
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/* FTPAN helper functions */
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static bool ftpan_32(void);
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static bool ftpan_37(void);
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static bool ftpan_36(void);
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#ifdef SOFTDEVICE_PRESENT
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#include "softdevice_handler.h"
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uint8_t _ble_evt_buffer[BLE_STACK_EVT_MSG_BUF_SIZE];
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#endif
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/**
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* @brief Initialize the CPU, set IRQ priorities
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*/
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void cpu_init(void)
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{
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/* Workaround for FTPAN-32
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* "DIF: Debug session automatically enables TracePort pins." */
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if (ftpan_32()) {
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CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
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}
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/* Workaround for FTPAN-37
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* "AMLI: EasyDMA is slow with Radio, ECB, AAR and CCM." */
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if (ftpan_37()) {
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*(volatile uint32_t *)0x400005A0 = 0x3;
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}
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/* Workaround for FTPAN-36
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* "CLOCK: Some registers are not reset when expected." */
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if (ftpan_36()) {
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NRF_CLOCK->EVENTS_DONE = 0;
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NRF_CLOCK->EVENTS_CTTO = 0;
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}
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/* initialize hf clock */
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clock_init_hf();
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/* softdevice needs to be enabled from ISR context */
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#ifdef SOFTDEVICE_PRESENT
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softdevice_handler_init(NRF_CLOCK_LFCLKSRC_XTAL_20_PPM, &_ble_evt_buffer,
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BLE_STACK_EVT_MSG_BUF_SIZE, NULL);
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/* fixup swi0 (used as softdevice PendSV trampoline) */
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NVIC_EnableIRQ(SWI0_EGU0_IRQn);
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NVIC_SetPriority(SWI0_EGU0_IRQn, 6);
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#else
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/* call cortexm default initialization */
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cortexm_init();
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#endif
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/* enable wake up on events for __WFE CPU sleep */
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SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
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/* trigger static peripheral initialization */
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periph_init();
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}
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/**
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* @brief Check workaround for FTPAN-32
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*/
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static bool ftpan_32(void)
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{
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if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6)
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&& (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
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&& (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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/**
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* @brief Check workaround for FTPAN-36
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*/
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static bool ftpan_36(void)
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{
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if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6)
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&& (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
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&& (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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/**
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* @brief Check workaround for FTPAN-37
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*/
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static bool ftpan_37(void)
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{
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if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6)
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&& (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) {
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if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
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&& (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) {
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return true;
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}
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}
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return false;
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}
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