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b57ce103a3
When redoing the SPI driver for the msp430 platforms an assert statement was introduced to prohibit SPI access without any buffers. Since in the existing code the FIFO pointer is incremented through a dummy read this results in triggering aforementioned assert.
251 lines
7.3 KiB
C
251 lines
7.3 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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* 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup drivers_cc2420
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* @{
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*
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* @file
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* @brief Implementation of public functions for cc2420 driver
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*
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "periph/cpuid.h"
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#include "byteorder.h"
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#include "net/ieee802154.h"
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#include "net/gnrc.h"
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#include "cc2420_internal.h"
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#include "cc2420_netdev.h"
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#include "cc2420_registers.h"
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#define ENABLE_DEBUG (0)
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#include "debug.h"
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/**
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* @todo Move this function to a global module
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*/
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#if CPUID_ID_LEN
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static void addr_from_cpuid(uint8_t *addr)
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{
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/* option 1: generate addresses from CPUID */
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uint8_t cpuid[CPUID_ID_LEN];
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cpuid_get(cpuid);
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memcpy(addr, cpuid, 8);
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#if CPUID_ID_LEN < 8
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/* in case CPUID_ID_LEN < 8, fill missing bytes with zeros */
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for (int i = CPUID_ID_LEN; i < 8; i++) {
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addr_long[i] = 0;
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}
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#else
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/* in case CPUID_ID_LEN > 8, XOR those bytes on top of the first 8 */
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for (int i = 8; i < CPUID_ID_LEN; i++) {
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addr_long[i & 0x07] ^= cpuid[i];
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}
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#endif
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/* make sure we mark the address as non-multicast and not globally unique */
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addr_long[0] &= ~(0x01);
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addr_long[0] |= 0x02;
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}
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#endif
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void cc2420_setup(cc2420_t * dev, const cc2420_params_t *params)
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{
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/* set pointer to the devices netdev functions */
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dev->netdev.netdev.driver = &cc2420_driver;
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/* pull in device configuration parameters */
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memcpy(&dev->params, params, sizeof(cc2420_params_t));
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dev->state = CC2420_STATE_IDLE;
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/* reset device descriptor fields */
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dev->options = 0;
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spi_init_master(dev->params.spi, SPI_CONF_FIRST_RISING, dev->params.spi_clk);
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}
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int cc2420_init(cc2420_t *dev)
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{
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uint16_t reg;
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uint8_t addr[8] = CC2420_ADDR_FALLBACK;
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/* reset options and sequence number */
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dev->netdev.seq = 0;
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dev->netdev.flags = 0;
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/* set default address, channel, PAN ID, and TX power */
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#if CPUID_ID_LEN
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addr_from_cpuid(addr);
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#endif
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cc2420_set_addr_short(dev, &addr[6]);
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cc2420_set_addr_long(dev, addr);
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cc2420_set_pan(dev, CC2420_PANID_DEFAULT);
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cc2420_set_chan(dev, CC2420_CHAN_DEFAULT);
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cc2420_set_txpower(dev, CC2420_TXPOWER_DEFAULT);
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/* set default options */
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cc2420_set_option(dev, CC2420_OPT_AUTOACK, true);
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cc2420_set_option(dev, CC2420_OPT_CSMA, true);
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cc2420_set_option(dev, CC2420_OPT_TELL_TX_START, true);
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cc2420_set_option(dev, CC2420_OPT_TELL_RX_END, true);
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#ifdef MODULE_NETSTATS_L2
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cc2420_set_option(dev, CC2420_OPT_TELL_RX_END, true);
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#endif
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/* set default protocol*/
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#ifdef MODULE_GNRC_SIXLOWPAN
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dev->netdev.proto = GNRC_NETTYPE_SIXLOWPAN;
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#elif MODULE_GNRC
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dev->netdev.proto = GNRC_NETTYPE_UNDEF;
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#endif
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/* change default RX bandpass filter to 1.3uA (as recommended) */
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reg = cc2420_reg_read(dev, CC2420_REG_RXCTRL1);
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reg |= CC2420_RXCTRL1_RXBPF_LOCUR;
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cc2420_reg_write(dev, CC2420_REG_RXCTRL1, reg);
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/* set the FIFOP threshold to maximum. */
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cc2420_reg_write(dev, CC2420_REG_IOCFG0, CC2420_PKT_MAXLEN);
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/* turn off "Security enable" (page 33). */
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reg = cc2420_reg_read(dev, CC2420_REG_SECCTRL0);
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reg &= ~CC2420_SECCTRL0_RXFIFO_PROT;
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cc2420_reg_write(dev, CC2420_REG_SECCTRL0, reg);
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/* go into RX state */
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cc2420_set_state(dev, CC2420_GOTO_RX);
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/* set preamble length to 3 leading zero byte */
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reg = cc2420_reg_read(dev, CC2420_REG_MDMCTRL0);
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reg &= ~(CC2420_MDMCTRL0_PREAMBLE_M);
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reg |= CC2420_MDMCTRL0_PREAMBLE_3B;
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cc2420_reg_write(dev, CC2420_REG_MDMCTRL0, reg);
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return 0;
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}
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bool cc2420_cca(cc2420_t *dev)
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{
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while (!(cc2420_status(dev) & CC2420_STATUS_RSSI_VALID)) {}
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return gpio_read(dev->params.pin_cca);
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}
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size_t cc2420_send(cc2420_t *dev, const struct iovec *data, unsigned count)
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{
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size_t n = cc2420_tx_prepare(dev, data, count);
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if ((n > 0) && !(dev->options & CC2420_OPT_PRELOADING)) {
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cc2420_tx_exec(dev);
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}
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return n;
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}
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size_t cc2420_tx_prepare(cc2420_t *dev, const struct iovec *data, unsigned count)
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{
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size_t pkt_len = 2; /* include the FCS (frame check sequence) */
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/* wait for any ongoing transmissions to be finished */
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while (cc2420_get_state(dev) & NETOPT_STATE_TX) {}
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/* get and check the length of the packet */
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for (unsigned i = 0; i < count; i++) {
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pkt_len += data[i].iov_len;
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}
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if (pkt_len >= CC2420_PKT_MAXLEN) {
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DEBUG("cc2420: tx_prep: unable to send, pkt too large\n");
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return 0;
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}
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/* flush TX FIFO and write new packet to it */
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cc2420_strobe(dev, CC2420_STROBE_FLUSHTX);
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/* push packet length to TX FIFO */
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cc2420_fifo_write(dev, (uint8_t *)&pkt_len, 1);
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/* push packet to TX FIFO */
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for (int i = 0; i < count; i++) {
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cc2420_fifo_write(dev, (uint8_t *)data[i].iov_base, data[i].iov_len);
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}
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DEBUG("cc2420: tx_prep: loaded %i byte into the TX FIFO\n", (int)pkt_len);
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return pkt_len;
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}
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void cc2420_tx_exec(cc2420_t *dev)
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{
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/* make sure, any ongoing transmission is finished */
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DEBUG("cc2420: tx_exec: waiting for any ongoing transmission\n");
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while (cc2420_get_state(dev) & NETOPT_STATE_TX) {}
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/* trigger the transmission */
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if (dev->options & CC2420_OPT_TELL_TX_START) {
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dev->netdev.netdev.event_callback(&dev->netdev.netdev,
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NETDEV2_EVENT_TX_STARTED);
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}
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DEBUG("cc2420: tx_exec: TX_START\n");
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if (dev->options & CC2420_OPT_CSMA) {
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DEBUG("cc2420: tx_exec: triggering TX with CCA\n");
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cc2420_strobe(dev, CC2420_STROBE_TXONCCA);
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}
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else {
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DEBUG("cc2420: tx_exec: triggering TX without CCA\n");
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cc2420_strobe(dev, CC2420_STROBE_TXON);
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}
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while (gpio_read(dev->params.pin_sfd)) {
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puts("\t...ongoing}");
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}
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if (dev->options & CC2420_OPT_TELL_TX_END) {
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dev->netdev.netdev.event_callback(&dev->netdev.netdev,
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NETDEV2_EVENT_TX_COMPLETE);
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}
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DEBUG("cc2420: tx_exec: TX_DONE\n");
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}
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int cc2420_rx(cc2420_t *dev, uint8_t *buf, size_t max_len, void *info)
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{
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uint8_t len;
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/* get the packet length (without dropping it) (first byte in RX FIFO) */
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cc2420_ram_read(dev, CC2420_RAM_RXFIFO, &len, 1);
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len -= 2; /* subtract RSSI and FCF */
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if (!buf) {
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DEBUG("cc2420: recv: packet of length %i in RX FIFO\n", (int)len);
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}
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/* if a buffer is given, read (and drop) the packet */
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if (buf) {
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/* We could the drop length byte here, msp430 platforms don't allow
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* empty reads so we don't do it and read the length byte again. */
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cc2420_fifo_read(dev, &len, 1);
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len -=2; /* subtract RSSI and FCF */
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len = (len > max_len) ? max_len : len;
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/* read fifo contents */
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DEBUG("cc2420: recv: reading %i byte of the packet\n", (int)len);
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cc2420_fifo_read(dev, buf, len);
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uint8_t rssi;
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cc2420_fifo_read(dev, &rssi, 1);
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DEBUG("cc2420: recv: RSSI is %i\n", (int)rssi);
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/* finally flush the FIFO */
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cc2420_strobe(dev, CC2420_STROBE_FLUSHRX);
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cc2420_strobe(dev, CC2420_STROBE_FLUSHRX);
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}
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return (int)len;
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}
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