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https://github.com/RIOT-OS/RIOT.git
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124 lines
3.3 KiB
C
124 lines
3.3 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_nucleo-f334
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the nucleo-f334 board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Kaspar Schleiser <kaspar.schleiser@fu-berlin.de>
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*/
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#ifndef PERIPH_CONF_H_
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#define PERIPH_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock system configuration
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* @{
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**/
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#define CLOCK_HSE (8000000U) /* external oscillator */
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#define CLOCK_CORECLOCK (72000000U) /* desired core clock frequency */
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/* the actual PLL values are automatically generated */
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#define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSE)
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV2
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#define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY_1
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/** @} */
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/**
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* @brief DAC configuration
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* @{
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*/
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#define DAC_NUMOF (0)
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/** @} */
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/**
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* @brief Timer configuration
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* @{
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*/
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#define TIMER_NUMOF (1U)
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#define TIMER_0_EN 1
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#define TIMER_IRQ_PRIO 1
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/* Timer 0 configuration */
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#define TIMER_0_DEV TIM2
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#define TIMER_0_CHANNELS 4
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#define TIMER_0_FREQ (CLOCK_CORECLOCK)
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#define TIMER_0_MAX_VALUE (0xffffffff)
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#define TIMER_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_TIM2EN)
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#define TIMER_0_ISR isr_tim2
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#define TIMER_0_IRQ_CHAN TIM2_IRQn
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/** @} */
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/**
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* @brief UART configuration
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* @}
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*/
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#define UART_NUMOF (1U)
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#define UART_0_EN 1
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#define UART_IRQ_PRIO 1
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/* UART 0 device configuration */
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#define UART_0_DEV USART2
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#define UART_0_CLKEN() (RCC->APB1ENR |= RCC_APB1ENR_USART2EN)
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#define UART_0_CLK (CLOCK_CORECLOCK / 2) /* UART clock runs with 32MHz (F_CPU / 1) */
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#define UART_0_IRQ_CHAN USART2_IRQn
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#define UART_0_ISR isr_usart2
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/* UART 0 pin configuration */
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#define UART_0_PORT GPIOA
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#define UART_0_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define UART_0_RX_PIN 3
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#define UART_0_TX_PIN 2
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#define UART_0_AF 7
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/** @} */
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/**
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* @name SPI configuration
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* @{
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*/
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#define SPI_NUMOF (1U)
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#define SPI_0_EN 1
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#define SPI_IRQ_PRIO 1
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/* SPI 0 device config */
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#define SPI_0_DEV SPI1
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#define SPI_0_CLKEN() (RCC->APB2ENR |= RCC_APB2ENR_SPI1EN)
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#define SPI_0_CLKDIS() (RCC->APB2ENR &= ~RCC_APB2ENR_SPI1EN)
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#define SPI_0_IRQ SPI1_IRQn
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#define SPI_0_IRQ_HANDLER isr_spi1
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/* SPI 0 pin configuration */
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#define SPI_0_SCK_PORT GPIOA
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#define SPI_0_SCK_PIN 5
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#define SPI_0_SCK_AF 5
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#define SPI_0_SCK_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MISO_PORT GPIOA
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#define SPI_0_MISO_PIN 6
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#define SPI_0_MISO_AF 5
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#define SPI_0_MISO_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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#define SPI_0_MOSI_PORT GPIOA
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#define SPI_0_MOSI_PIN 7
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#define SPI_0_MOSI_AF 5
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#define SPI_0_MOSI_PORT_CLKEN() (RCC->AHBENR |= RCC_AHBENR_GPIOAEN)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H_ */
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/** @} */
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