mirror of
https://github.com/RIOT-OS/RIOT.git
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e7fbaf3815
- removed the __attribute__((naked)) from ISRs - removed ISR_ENTER() and ISR_EXIT() macros Rationale: Cortex-Mx MCUs save registers R0-R4 automatically on calling ISRs. The naked attribute tells the compiler not to save any other registers. This is fine, as long as the code in the ISR is not nested. If nested, it will use also R4 and R5, which will then lead to currupted registers on exit of the ISR. Removing the naked will fix this.
477 lines
9.4 KiB
C
477 lines
9.4 KiB
C
/*
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* Copyright (C) 2014 Loci Controls Inc.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup driver_periph
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* @{
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*
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* @file timer.c
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* @brief Low-level timer driver implementation for the CC2538 CPU
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*
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* @author Ian Martin <ian@locicontrols.com>
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*
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* @}
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*/
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#include <stdlib.h>
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#include <stdio.h>
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#include "board.h"
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#include "cpu.h"
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#include "sched.h"
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#include "thread.h"
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#include "periph/timer.h"
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#include "periph_conf.h"
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#define USEC_PER_SEC 1000000 /**< Conversion factor between seconds and microseconds */
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typedef struct {
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void (*cb)(int);
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} timer_conf_t;
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/**
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* @brief Timer state memory
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*/
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timer_conf_t config[TIMER_NUMOF];
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/**
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* @brief Setup the given timer
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*
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*/
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int timer_init(tim_t dev, unsigned int ticks_per_us, void (*callback)(int))
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{
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cc2538_gptimer_t *gptimer;
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unsigned int gptimer_num;
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/* select the timer and enable the timer specific peripheral clocks */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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gptimer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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gptimer = TIMER_1_DEV;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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gptimer = TIMER_2_DEV;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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gptimer = TIMER_3_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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gptimer_num = ((uintptr_t)gptimer - (uintptr_t)GPTIMER0) / 0x1000;
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/* Save the callback function: */
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config[dev].cb = callback;
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/* Enable the clock for this timer: */
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SYS_CTRL_RCGCGPT |= (1 << gptimer_num);
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/* Disable this timer before configuring it: */
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gptimer->CTL = 0;
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gptimer->CFG = GPTMCFG_16_BIT_TIMER;
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gptimer->TAMR = GPTIMER_PERIODIC_MODE;
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gptimer->TAMRbits.TACDIR = 1; /**< Count up */
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/* Set the prescale register for the desired frequency: */
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gptimer->TAPR = RCOSC16M_FREQ / (ticks_per_us * USEC_PER_SEC) - 1;
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/* Enable interrupts for given timer: */
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timer_irq_enable(dev);
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/* Enable the timer: */
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gptimer->CTLbits.TAEN = 1;
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return 0;
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}
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int timer_set(tim_t dev, int channel, unsigned int timeout)
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{
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return timer_set_absolute(dev, channel, timer_read(dev) + timeout);
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}
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int timer_set_absolute(tim_t dev, int channel, unsigned int value)
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{
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cc2538_gptimer_t *gptimer;
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/* get timer base register address */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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gptimer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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gptimer = TIMER_1_DEV;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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gptimer = TIMER_2_DEV;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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gptimer = TIMER_3_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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/* set timeout value */
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switch (channel) {
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case 0:
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gptimer->TAILR = value;
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break;
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case 1:
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gptimer->TBILR = value;
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break;
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default:
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return -1;
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}
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return 1;
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}
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int timer_clear(tim_t dev, int channel)
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{
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cc2538_gptimer_t *gptimer;
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/* get timer base register address */
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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gptimer = TIMER_0_DEV;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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gptimer = TIMER_1_DEV;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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gptimer = TIMER_2_DEV;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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gptimer = TIMER_3_DEV;
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return -1;
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}
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switch (channel) {
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case 0:
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gptimer->CTLbits.TAEN = 0;
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break;
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case 1:
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gptimer->CTLbits.TBEN = 0;
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break;
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default:
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return -1;
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}
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return 1;
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}
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/*
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* The timer channels 1 and 2 are configured to run with the same speed and
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* have the same value (they run in parallel), so only on of them is returned.
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*/
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unsigned int timer_read(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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return TIMER_0_DEV->TAR;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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return TIMER_1_DEV->TAR;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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return TIMER_2_DEV->TAR;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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return TIMER_3_DEV->TAR;
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#endif
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case TIMER_UNDEFINED:
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default:
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return 0;
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}
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}
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/*
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* For stopping the counting of all channels.
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*/
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void timer_stop(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER_0_DEV->CTLbits.TAEN = 0;
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TIMER_0_DEV->CTLbits.TBEN = 0;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER_1_DEV->CTLbits.TAEN = 0;
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TIMER_1_DEV->CTLbits.TBEN = 0;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER_2_DEV->CTLbits.TAEN = 0;
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TIMER_2_DEV->CTLbits.TBEN = 0;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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TIMER_3_DEV->CTLbits.TAEN = 0;
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TIMER_3_DEV->CTLbits.TBEN = 0;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_start(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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TIMER_0_DEV->CTLbits.TAEN = 1;
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TIMER_0_DEV->CTLbits.TBEN = 1;
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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TIMER_1_DEV->CTLbits.TAEN = 1;
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TIMER_1_DEV->CTLbits.TBEN = 1;
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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TIMER_2_DEV->CTLbits.TAEN = 1;
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TIMER_2_DEV->CTLbits.TBEN = 1;
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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TIMER_3_DEV->CTLbits.TAEN = 1;
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TIMER_3_DEV->CTLbits.TBEN = 1;
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break;
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#endif
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case TIMER_UNDEFINED:
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break;
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}
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}
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void timer_irq_enable(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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NVIC_SetPriority(TIMER_0_IRQn_1, TIMER_IRQ_PRIO);
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NVIC_SetPriority(TIMER_0_IRQn_2, TIMER_IRQ_PRIO);
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NVIC_EnableIRQ(TIMER_0_IRQn_1);
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NVIC_EnableIRQ(TIMER_0_IRQn_2);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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NVIC_SetPriority(TIMER_1_IRQn_1, TIMER_IRQ_PRIO);
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NVIC_SetPriority(TIMER_1_IRQn_2, TIMER_IRQ_PRIO);
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NVIC_EnableIRQ(TIMER_1_IRQn_1);
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NVIC_EnableIRQ(TIMER_1_IRQn_2);
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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NVIC_SetPriority(TIMER_2_IRQn_1, TIMER_IRQ_PRIO);
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NVIC_SetPriority(TIMER_2_IRQn_2, TIMER_IRQ_PRIO);
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NVIC_EnableIRQ(TIMER_2_IRQn_1);
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NVIC_EnableIRQ(TIMER_2_IRQn_2);
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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NVIC_SetPriority(TIMER_3_IRQn_1, TIMER_IRQ_PRIO);
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NVIC_SetPriority(TIMER_3_IRQn_2, TIMER_IRQ_PRIO);
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NVIC_EnableIRQ(TIMER_3_IRQn_1);
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NVIC_EnableIRQ(TIMER_3_IRQn_2);
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return;
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}
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}
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void timer_irq_disable(tim_t dev)
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{
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switch (dev) {
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#if TIMER_0_EN
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case TIMER_0:
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NVIC_DisableIRQ(TIMER_0_IRQn_1);
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NVIC_DisableIRQ(TIMER_0_IRQn_2);
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break;
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#endif
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#if TIMER_1_EN
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case TIMER_1:
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NVIC_DisableIRQ(TIMER_1_IRQn_1);
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NVIC_DisableIRQ(TIMER_1_IRQn_2);
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break;
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#endif
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#if TIMER_2_EN
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case TIMER_2:
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NVIC_DisableIRQ(TIMER_2_IRQn_1);
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NVIC_DisableIRQ(TIMER_2_IRQn_2);
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break;
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#endif
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#if TIMER_3_EN
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case TIMER_3:
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NVIC_DisableIRQ(TIMER_3_IRQn_1);
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NVIC_DisableIRQ(TIMER_3_IRQn_2);
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break;
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#endif
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case TIMER_UNDEFINED:
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default:
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return;
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}
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}
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void timer_reset(tim_t dev)
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{
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timer_set_absolute(dev, 0, 0);
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timer_set_absolute(dev, 1, 0);
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}
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#if TIMER_0_EN
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void TIMER_0_ISR_1(void)
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{
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if (config[0].cb != NULL) config[0].cb(0);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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void TIMER_0_ISR_2(void)
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{
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if (config[0].cb != NULL) config[0].cb(1);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif /* TIMER_0_EN */
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#if TIMER_1_EN
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void TIMER_1_ISR_1(void)
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{
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if (config[1].cb != NULL) config[1].cb(0);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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void TIMER_1_ISR_2(void)
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{
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if (config[1].cb != NULL) config[1].cb(1);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif /* TIMER_1_EN */
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#if TIMER_2_EN
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void TIMER_2_ISR_1(void)
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{
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if (config[2].cb != NULL) config[2].cb(0);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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void TIMER_2_ISR_2(void)
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{
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if (config[2].cb != NULL) config[2].cb(1);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif /* TIMER_2_EN */
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#if TIMER_3_EN
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void TIMER_3_ISR_1(void)
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{
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if (config[3].cb != NULL) config[3].cb(0);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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void TIMER_3_ISR_2(void)
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{
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if (config[3].cb != NULL) config[3].cb(1);
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if (sched_context_switch_request) {
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thread_yield();
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}
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}
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#endif /* TIMER_3_EN */
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