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7d1d5e77d8
New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools
24 lines
534 B
C
24 lines
534 B
C
// See LICENSE for license details.
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#ifndef _SIFIVE_OTP_H
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#define _SIFIVE_OTP_H
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/* Register offsets */
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#define OTP_LOCK 0x00
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#define OTP_CK 0x04
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#define OTP_OE 0x08
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#define OTP_SEL 0x0C
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#define OTP_WE 0x10
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#define OTP_MR 0x14
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#define OTP_MRR 0x18
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#define OTP_MPP 0x1C
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#define OTP_VRREN 0x20
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#define OTP_VPPEN 0x24
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#define OTP_A 0x28
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#define OTP_D 0x2C
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#define OTP_Q 0x30
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#define OTP_READ_TIMINGS 0x34
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#endif
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