Koen Zandberg 0a6c9c4ec0 stdio_semihosting: Extend with RISC-V support ... RISC-V support semihosting in very similar way as the cortex-m microcontrollers. The code calls a breakpoint instruction and the attached debugger reads/writes registers and memory for stdio. The RISC-V architecture doesn't support a call number with the EBREAK instruction, to allow the debugger to detect a semihosting break point, the EBREAK instruction is wrapped in a SLLI and SRAI instruction. These use x0 as output register, making them NOP instructions. One caveat when using this is that the RISC-V core traps the EBREAK instruction with trap code 3 when no debugger is attached. Restarting the application with the debugger attached avoids this.		2021-01-27 17:52:19 +01:00
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Makefile	stdio_semihosting: Initial include of Semihosting-based STDIO	2020-06-09 10:15:49 +02:00
stdio_semihosting.c	stdio_semihosting: Extend with RISC-V support	2021-01-27 17:52:19 +01:00