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https://github.com/RIOT-OS/RIOT.git
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db4d67c4fd
Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua
136 lines
3.8 KiB
C
136 lines
3.8 KiB
C
/*
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* Copyright (C) 2017 JP Bonn
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_fe310
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* @{
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*
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* @file
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* @brief Thread context frame stored on stack.
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*
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* @author JP Bonn
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*/
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#ifndef CONTEXT_FRAME_H
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#define CONTEXT_FRAME_H
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#if !defined(__ASSEMBLER__)
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#include <stdint.h>
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#include <assert.h>
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#endif /* __ASSEMBLER__ */
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if !defined(__ASSEMBLER__)
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/**
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* @brief Stores the registers and PC for a context switch.
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*
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* This also defines context_switch_frame offsets for assembly language. The
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* structure is sized to maintain 16 byte stack alignment per the ABI.
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* https://github.com/riscv/riscv-elf-psabi-doc
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*
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*/
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struct context_switch_frame {
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uint32_t pad[2]; /**< padding to maintain 16 byte alignment */
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uint32_t pc; /**< program counter */
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/* Callee saved registers */
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uint32_t s0; /**< s0 register */
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uint32_t s1; /**< s1 register */
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uint32_t s2; /**< s2 register */
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uint32_t s3; /**< s3 register */
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uint32_t s4; /**< s4 register */
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uint32_t s5; /**< s5 register */
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uint32_t s6; /**< s6 register */
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uint32_t s7; /**< s7 register */
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uint32_t s8; /**< s8 register */
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uint32_t s9; /**< s9 register */
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uint32_t s10; /**< s10 register */
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uint32_t s11; /**< s11 register */
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/* Caller saved registers */
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uint32_t ra; /**< ra register */
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uint32_t tp; /**< tp register */
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uint32_t t0; /**< t0 register */
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uint32_t t1; /**< t1 register */
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uint32_t t2; /**< t2 register */
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uint32_t t3; /**< t3 register */
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uint32_t t4; /**< t4 register */
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uint32_t t5; /**< t5 register */
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uint32_t t6; /**< t6 register */
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uint32_t a0; /**< a0 register */
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uint32_t a1; /**< a1 register */
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uint32_t a2; /**< a2 register */
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uint32_t a3; /**< a3 register */
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uint32_t a4; /**< a4 register */
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uint32_t a5; /**< a5 register */
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uint32_t a6; /**< a6 register */
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uint32_t a7; /**< a7 register */
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};
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#endif /* __ASSEMBLER__ */
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/**
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* @name Register offsets
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* @{
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*/
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/* These values are checked for correctness in context_frame.c */
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#define pad_OFFSET 0
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#define pc_OFFSET 8
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#define s0_OFFSET 12
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#define s1_OFFSET 16
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#define s2_OFFSET 20
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#define s3_OFFSET 24
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#define s4_OFFSET 28
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#define s5_OFFSET 32
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#define s6_OFFSET 36
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#define s7_OFFSET 40
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#define s8_OFFSET 44
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#define s9_OFFSET 48
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#define s10_OFFSET 52
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#define s11_OFFSET 56
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#define ra_OFFSET 60
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#define tp_OFFSET 64
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#define t0_OFFSET 68
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#define t1_OFFSET 72
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#define t2_OFFSET 76
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#define t3_OFFSET 80
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#define t4_OFFSET 84
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#define t5_OFFSET 88
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#define t6_OFFSET 92
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#define a0_OFFSET 96
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#define a1_OFFSET 100
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#define a2_OFFSET 104
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#define a3_OFFSET 108
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#define a4_OFFSET 112
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#define a5_OFFSET 116
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#define a6_OFFSET 120
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#define a7_OFFSET 124
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/** @} */
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/**
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* @brief Size of context switch frame
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*/
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#define CONTEXT_FRAME_SIZE (a7_OFFSET + 4)
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/**
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* @brief Offset of stack pointer in struct _thread
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*/
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#define SP_OFFSET_IN_THREAD 0
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#ifdef __cplusplus
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}
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#endif
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#endif /* CONTEXT_FRAME_H */
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/** @} */
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