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71 lines
1.4 KiB
C
71 lines
1.4 KiB
C
/*
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* Copyright(C) 2017, 2016, Imagination Technologies Limited and/or its
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* affiliated group companies.
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*
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*/
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/**
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* @defgroup cpu_mips32r2_common Imagination Technologies MIPS32R2 Common
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* @ingroup cpu
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* @brief CPU definitions for MIPS32R2 devices.
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* @{
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*
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* @file
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* @brief CPU definitions for MIPS32R2 devices.
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*
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* @author Neil Jones <neil.jones@imgtec.com>
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*/
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#ifndef CPU_H
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#define CPU_H
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#include <stdint.h>
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#include "cpu_conf.h"
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#include "thread.h"
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#include "irq.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Select fastest bitarithm_lsb implementation
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* @{
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*/
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#define BITARITHM_LSB_BUILTIN
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#define BITARITHM_HAS_CLZ
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/** @} */
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/**
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* @brief Print the last instruction's address
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*
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* @todo: Not supported
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*/
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static inline void cpu_print_last_instruction(void)
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{
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/* This function must exist else RIOT won't compile */
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}
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/**
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* @brief Trigger a conditional context scheduler run / context switch
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*
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* This function is supposed to be called in the end of each ISR.
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*/
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static inline void mips32r2_isr_end(void)
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{
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if (sched_context_switch_request) {
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thread_yield_higher();
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}
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* CPU_H */
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/** @} */
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