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3f59eefbaf
Creating all object files in one directory is bound to produce name clashes. RIOT developers may take care to use unique file names, but external packages surely don't. With this change all the objects of a module (e.g. `shell`) will be created in `bin/$(BOARD)/$(MODULE)`. I compared the final linker command before and after the change. The `.o` files (e.g. `startup.o`, `syscall.o` ...) are included in the same order. Neglecting the changed path name where the `.o` files reside, the linker command stays exactly the same. A major problem could be third party boards, because the location of the `startup.o` needs to the specified now in `boards/$(BOARD)/Makefile.include`, e.g. ```Makefile export UNDEF += $(BINDIR)msp430_common/startup.o ```
38 lines
1.2 KiB
Makefile
38 lines
1.2 KiB
Makefile
include $(RIOTBOARD)/$(BOARD)/Makefile.dep
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## the cpu to build for
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export CPU = msp430x16x
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export MCU = msp430f1611
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# toolchain config
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export PREFIX = msp430-
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export CC = $(PREFIX)gcc
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export AR = $(PREFIX)ar
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export CFLAGS += -Wstrict-prototypes -gdwarf-2 -Os -Wall -mmcu=$(MCU)
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export ASFLAGS += -mmcu=$(MCU) --defsym $(MCU)=1 --gdwarf-2
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export AS = $(PREFIX)as
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export LINK = $(PREFIX)gcc
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export SIZE = $(PREFIX)size
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export OBJCOPY = $(PREFIX)objcopy
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export LINKFLAGS = -mmcu=$(MCU) -lgcc $(BINDIR)msp430_common/startup.o
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export TERMPROG = $(RIOTBASE)/dist/tools/pyterm/pyterm.py
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export FLASHER = goodfet.bsl
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ifeq ($(strip $(PORT)),)
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export PORT = /dev/ttyUSB0
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endif
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export HEXFILE = $(BINDIR)$(PROJECT).hex
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export FFLAGS = --telosb -c $(PORT) -r -e -I -p $(HEXFILE)
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export INCLUDES += -I$(RIOTCPU)/msp430-common/include -I$(RIOTBOARD)/$(BOARD)/include -I$(RIOTBASE)/drivers/cc2420/include -I$(RIOTBASE)/sys/net/include
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export OFLAGS = -O ihex
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ifneq (,$(filter defaulttransceiver,$(USEMODULE)))
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ifeq (,$(filter cc2240,$(USEMODULE)))
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USEMODULE += cc2420
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endif
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ifeq (,$(filter transceiver,$(USEMODULE)))
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USEMODULE += transceiver
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endif
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endif
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export UNDEF += $(BINDIR)msp430_common/startup.o
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