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https://github.com/RIOT-OS/RIOT.git
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131 lines
3.9 KiB
C
131 lines
3.9 KiB
C
/*
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* Copyright (C) 2021 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_stm32
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* @{
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*
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* @file
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* @brief Default STM32U5 clock configuration
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef CLK_U5_CFG_CLOCK_DEFAULT_H
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#define CLK_U5_CFG_CLOCK_DEFAULT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name U5 clock system configuration
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* @{
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*/
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && (CONFIG_CLOCK_HSE < MHZ(4) || CONFIG_CLOCK_HSE > MHZ(48))
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#error "HSE clock frequency must be between 4MHz and 48MHz"
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#endif
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/* The following parameters configure a 80MHz system clock with PLL as input clock */
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#ifndef CONFIG_CLOCK_PLL_SRC_MSI
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE) || IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) || \
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IS_ACTIVE(CONFIG_BOARD_HAS_HSE)
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#define CONFIG_CLOCK_PLL_SRC_MSI 0
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#else
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#define CONFIG_CLOCK_PLL_SRC_MSI 1 /* Use MSI as input clock by default */
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#endif
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#endif /* CONFIG_CLOCK_PLL_SRC_MSI */
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#ifndef CONFIG_CLOCK_PLL_SRC_HSE
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#if IS_ACTIVE(CONFIG_BOARD_HAS_HSE) && \
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!IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSI) && !IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CONFIG_CLOCK_PLL_SRC_HSE 1
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#else
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#define CONFIG_CLOCK_PLL_SRC_HSE 0
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_SRC_HSI
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#define CONFIG_CLOCK_PLL_SRC_HSI 0
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#endif
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_MSI)
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#elif IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_HSE)
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSE)
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#else /* CONFIG_CLOCK_PLL_SRC_ */
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#define CLOCK_PLL_SRC (CONFIG_CLOCK_HSI)
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#endif
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#ifndef CONFIG_CLOCK_PLL_M
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#if IS_ACTIVE(CONFIG_CLOCK_PLL_SRC_MSI)
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#define CONFIG_CLOCK_PLL_M (6) /* MSI at 48MHz */
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#else
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#define CONFIG_CLOCK_PLL_M (2) /* HSI/HSE at 16MHz */
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#endif
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#endif
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#ifndef CONFIG_CLOCK_PLL_N
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#define CONFIG_CLOCK_PLL_N (40)
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#endif
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#ifndef CONFIG_CLOCK_PLL_Q
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#define CONFIG_CLOCK_PLL_Q (2)
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#endif
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#ifndef CONFIG_CLOCK_PLL_R
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#define CONFIG_CLOCK_PLL_R (2)
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#endif
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#if IS_ACTIVE(CONFIG_USE_CLOCK_HSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_HSE)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
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#define CLOCK_CORECLOCK (CONFIG_CLOCK_MSI)
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#elif IS_ACTIVE(CONFIG_USE_CLOCK_PLL)
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/* PLL configuration: make sure your values are legit!
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*
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* compute by: CORECLOCK = (((PLL_IN / M) * N) / R)
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* with:
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* PLL_IN: input clock, HSE or MSI
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* M: pre-divider, allowed range: [1:8]
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* N: multiplier, allowed range: [5:512]
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* R: post-divider, allowed range: [2:8]
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*
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* Also the following constraints need to be met:
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* (PLL_IN / M) -> [4MHz:16MHz]
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* (PLL_IN / M) * N -> [64MHz:344MHz]
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* CORECLOCK -> 64MHz, 80MHZ or 120MHz MAX!
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*/
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#define CLOCK_CORECLOCK \
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((CLOCK_PLL_SRC / CONFIG_CLOCK_PLL_M) * CONFIG_CLOCK_PLL_N) / CONFIG_CLOCK_PLL_R
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/* Set max allowed sysclk */
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#define CLOCK_CORECLOCK_MAX MHZ(160)
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#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
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#error "SYSCLK cannot exceed 160MHz"
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#endif /* CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX */
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#endif /* CONFIG_USE_CLOCK_PLL */
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#define CLOCK_AHB CLOCK_CORECLOCK /* HCLK, max: 160MHz */
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#ifndef CONFIG_CLOCK_APB1_DIV
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#define CONFIG_CLOCK_APB1_DIV (4)
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#endif
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#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV) /* PCLK1, max: 160MHz */
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#ifndef CONFIG_CLOCK_APB2_DIV
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#define CONFIG_CLOCK_APB2_DIV (2)
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#endif
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#define CLOCK_APB2 (CLOCK_AHB / CONFIG_CLOCK_APB2_DIV) /* PCLK1, max: 160MHz */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* CLK_U5_CFG_CLOCK_DEFAULT_H */
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/** @} */
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