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191 lines
8.8 KiB
C
191 lines
8.8 KiB
C
/******************************************************************************
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* Filename: hw_rfc_rat_h
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* Revised: 2017-01-31 09:37:48 +0100 (Tue, 31 Jan 2017)
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* Revision: 48345
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*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1) Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3) Neither the name of the ORGANIZATION nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************/
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#ifndef __HW_RFC_RAT_H__
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#define __HW_RFC_RAT_H__
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//*****************************************************************************
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//
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// This section defines the register offsets of
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// RFC_RAT component
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//
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//*****************************************************************************
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// Radio Timer Counter Value
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#define RFC_RAT_O_RATCNT 0x00000004
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// Timer Channel 0 Capture/Compare Register
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#define RFC_RAT_O_RATCH0VAL 0x00000080
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// Timer Channel 1 Capture/Compare Register
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#define RFC_RAT_O_RATCH1VAL 0x00000084
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// Timer Channel 2 Capture/Compare Register
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#define RFC_RAT_O_RATCH2VAL 0x00000088
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// Timer Channel 3 Capture/Compare Register
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#define RFC_RAT_O_RATCH3VAL 0x0000008C
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// Timer Channel 4 Capture/Compare Register
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#define RFC_RAT_O_RATCH4VAL 0x00000090
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// Timer Channel 5 Capture/Compare Register
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#define RFC_RAT_O_RATCH5VAL 0x00000094
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// Timer Channel 6 Capture/Compare Register
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#define RFC_RAT_O_RATCH6VAL 0x00000098
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// Timer Channel 7 Capture/Compare Register
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#define RFC_RAT_O_RATCH7VAL 0x0000009C
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCNT
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//
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//*****************************************************************************
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// Field: [31:0] CNT
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//
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// Counter value. This is not writable while radio timer counter is enabled.
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#define RFC_RAT_RATCNT_CNT_W 32
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#define RFC_RAT_RATCNT_CNT_M 0xFFFFFFFF
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#define RFC_RAT_RATCNT_CNT_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH0VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH0VAL_VAL_W 32
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#define RFC_RAT_RATCH0VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH0VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH1VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH1VAL_VAL_W 32
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#define RFC_RAT_RATCH1VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH1VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH2VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH2VAL_VAL_W 32
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#define RFC_RAT_RATCH2VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH2VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH3VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH3VAL_VAL_W 32
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#define RFC_RAT_RATCH3VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH3VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH4VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH4VAL_VAL_W 32
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#define RFC_RAT_RATCH4VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH4VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH5VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH5VAL_VAL_W 32
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#define RFC_RAT_RATCH5VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH5VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH6VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH6VAL_VAL_W 32
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#define RFC_RAT_RATCH6VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH6VAL_VAL_S 0
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//*****************************************************************************
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//
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// Register: RFC_RAT_O_RATCH7VAL
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//
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//*****************************************************************************
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// Field: [31:0] VAL
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//
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// Capture/compare value. The system CPU can safely read this register, but it
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// is recommended to use the CPE API commands to configure it for compare mode.
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#define RFC_RAT_RATCH7VAL_VAL_W 32
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#define RFC_RAT_RATCH7VAL_VAL_M 0xFFFFFFFF
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#define RFC_RAT_RATCH7VAL_VAL_S 0
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#endif // __RFC_RAT__
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