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90 lines
2.9 KiB
C
90 lines
2.9 KiB
C
/*
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* Copyright (C) 2013 INRIA
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* Copyright (C) 2014 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_stm32f1
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* @{
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*
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* @file cpu.c
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* @brief Implementation of the kernel cpu functions
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*
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* @author Stefan Pfeiffer <stefan.pfeiffer@fu-berlin.de>
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* @author Alaeddine Weslati <alaeddine.weslati@inria.fr>
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* @author Thomas Eichinger <thomas.eichinger@fu-berlin.de>
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*
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* @}
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*/
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#include "cpu.h"
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#include "periph_conf.h"
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static void clk_init(void);
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void cpu_init(void)
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{
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/* set PendSV priority to the lowest possible priority */
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NVIC_SetPriority(PendSV_IRQn, 0xff);
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/* configure the vector table location to internal flash */
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SCB->VTOR = FLASH_BASE;
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/* initialize system clocks */
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clk_init();
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}
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/**
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* @brief Configure the clock system of the stm32f1
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*
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*/
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static void clk_init(void)
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{
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/* Reset the RCC clock configuration to the default reset state(for debug purpose) */
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/* Set HSION bit */
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RCC->CR |= (uint32_t)0x00000001;
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/* Reset SW, HPRE, PPRE1, PPRE2, ADCPRE and MCO bits */
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RCC->CFGR &= (uint32_t)0xF0FF0000;
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/* Reset HSEON, CSSON and PLLON bits */
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RCC->CR &= (uint32_t)0xFEF6FFFF;
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/* Reset HSEBYP bit */
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RCC->CR &= (uint32_t)0xFFFBFFFF;
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/* Reset PLLSRC, PLLXTPRE, PLLMUL and USBPRE/OTGFSPRE bits */
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RCC->CFGR &= (uint32_t)0xFF80FFFF;
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/* Disable all interrupts and clear pending bits */
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RCC->CIR = (uint32_t)0x009F0000;
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/* SYSCLK, HCLK, PCLK2 and PCLK1 configuration */
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/* Enable HSE */
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RCC->CR |= ((uint32_t)RCC_CR_HSEON);
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/* Wait till HSE is ready,
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* NOTE: the MCU will stay here forever if no HSE clock is connected */
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while ((RCC->CR & RCC_CR_HSERDY) == 0);
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/* Enable Prefetch Buffer */
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FLASH->ACR |= FLASH_ACR_PRFTBE;
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/* Flash 2 wait state */
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FLASH->ACR &= ~((uint32_t)FLASH_ACR_LATENCY);
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FLASH->ACR |= (uint32_t)CLOCK_FLASH_LATENCY;
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/* HCLK = SYSCLK */
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RCC->CFGR |= (uint32_t)CLOCK_AHB_DIV;
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/* PCLK2 = HCLK */
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RCC->CFGR |= (uint32_t)CLOCK_APB2_DIV;
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/* PCLK1 = HCLK */
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RCC->CFGR |= (uint32_t)CLOCK_APB1_DIV;
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/* PLL configuration: PLLCLK = HSE / HSE_DIV * HSE_MUL */
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RCC->CFGR &= ~((uint32_t)(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE | RCC_CFGR_PLLMULL));
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RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | CLOCK_PLL_HSE_DIV | CLOCK_PLL_HSE_MUL);
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/* Enable PLL */
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RCC->CR |= RCC_CR_PLLON;
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/* Wait till PLL is ready */
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while ((RCC->CR & RCC_CR_PLLRDY) == 0);
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/* Select PLL as system clock source */
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RCC->CFGR &= ~((uint32_t)(RCC_CFGR_SW));
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RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
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/* Wait till PLL is used as system clock source */
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while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL);
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}
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