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111 lines
6.4 KiB
C
111 lines
6.4 KiB
C
/**
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* \file
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*
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* \brief Instance description for MTB
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*
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* Copyright (c) 2014 Atmel Corporation. All rights reserved.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* 3. The name of Atmel may not be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* 4. This software may only be redistributed and used in connection with an
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* Atmel microcontroller product.
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*
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* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
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* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* \asf_license_stop
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*
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*/
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#ifndef _SAMR21_MTB_INSTANCE_
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#define _SAMR21_MTB_INSTANCE_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ========== Register definition for MTB peripheral ========== */
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#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_MTB_POSITION (0x41006000U) /**< \brief (MTB) MTB Position */
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#define REG_MTB_MASTER (0x41006004U) /**< \brief (MTB) MTB Master */
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#define REG_MTB_FLOW (0x41006008U) /**< \brief (MTB) MTB Flow */
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#define REG_MTB_BASE (0x4100600CU) /**< \brief (MTB) MTB Base */
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#define REG_MTB_ITCTRL (0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
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#define REG_MTB_CLAIMSET (0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
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#define REG_MTB_CLAIMCLR (0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
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#define REG_MTB_LOCKACCESS (0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
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#define REG_MTB_LOCKSTATUS (0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
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#define REG_MTB_AUTHSTATUS (0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
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#define REG_MTB_DEVARCH (0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
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#define REG_MTB_DEVID (0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
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#define REG_MTB_DEVTYPE (0x41006FCCU) /**< \brief (MTB) MTB Device Type */
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#define REG_MTB_PID4 (0x41006FD0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID5 (0x41006FD4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID6 (0x41006FD8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID7 (0x41006FDCU) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID0 (0x41006FE0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID1 (0x41006FE4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID2 (0x41006FE8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID3 (0x41006FECU) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID0 (0x41006FF0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID1 (0x41006FF4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID2 (0x41006FF8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID3 (0x41006FFCU) /**< \brief (MTB) CoreSight */
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#else
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#define REG_MTB_POSITION (*(RwReg *)0x41006000U) /**< \brief (MTB) MTB Position */
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#define REG_MTB_MASTER (*(RwReg *)0x41006004U) /**< \brief (MTB) MTB Master */
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#define REG_MTB_FLOW (*(RwReg *)0x41006008U) /**< \brief (MTB) MTB Flow */
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#define REG_MTB_BASE (*(RoReg *)0x4100600CU) /**< \brief (MTB) MTB Base */
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#define REG_MTB_ITCTRL (*(RwReg *)0x41006F00U) /**< \brief (MTB) MTB Integration Mode Control */
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#define REG_MTB_CLAIMSET (*(RwReg *)0x41006FA0U) /**< \brief (MTB) MTB Claim Set */
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#define REG_MTB_CLAIMCLR (*(RwReg *)0x41006FA4U) /**< \brief (MTB) MTB Claim Clear */
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#define REG_MTB_LOCKACCESS (*(RwReg *)0x41006FB0U) /**< \brief (MTB) MTB Lock Access */
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#define REG_MTB_LOCKSTATUS (*(RoReg *)0x41006FB4U) /**< \brief (MTB) MTB Lock Status */
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#define REG_MTB_AUTHSTATUS (*(RoReg *)0x41006FB8U) /**< \brief (MTB) MTB Authentication Status */
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#define REG_MTB_DEVARCH (*(RoReg *)0x41006FBCU) /**< \brief (MTB) MTB Device Architecture */
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#define REG_MTB_DEVID (*(RoReg *)0x41006FC8U) /**< \brief (MTB) MTB Device Configuration */
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#define REG_MTB_DEVTYPE (*(RoReg *)0x41006FCCU) /**< \brief (MTB) MTB Device Type */
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#define REG_MTB_PID4 (*(RoReg *)0x41006FD0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID5 (*(RoReg *)0x41006FD4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID6 (*(RoReg *)0x41006FD8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID7 (*(RoReg *)0x41006FDCU) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID0 (*(RoReg *)0x41006FE0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID1 (*(RoReg *)0x41006FE4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID2 (*(RoReg *)0x41006FE8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_PID3 (*(RoReg *)0x41006FECU) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID0 (*(RoReg *)0x41006FF0U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID1 (*(RoReg *)0x41006FF4U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID2 (*(RoReg *)0x41006FF8U) /**< \brief (MTB) CoreSight */
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#define REG_MTB_CID3 (*(RoReg *)0x41006FFCU) /**< \brief (MTB) CoreSight */
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#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _SAMR21_MTB_INSTANCE_ */
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