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152 lines
5.4 KiB
C
152 lines
5.4 KiB
C
/* esp/timer_regs.h
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*
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* ESP8266 Timer register definitions
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*
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* Not compatible with ESP SDK register access code.
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*/
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/*
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Copyright (c) 2015, SuperHouse Automation Pty Ltd
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef TIMER_REGS_H
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#define TIMER_REGS_H
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#ifndef DOXYGEN
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#include "esp/types.h"
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#include "common_macros.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define TIMER_BASE 0x60000600
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#define TIMER(i) (*(struct TIMER_REGS *)(TIMER_BASE + (i)*0x20))
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#define TIMER_FRC1 TIMER(0)
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#define TIMER_FRC2 TIMER(1)
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/* TIMER registers
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*
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* ESP8266 has two hardware timer counters, FRC1 and FRC2.
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*
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* FRC1 is a 24-bit countdown timer, triggers interrupt when reaches zero.
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* FRC2 is a 32-bit countup timer, can set a variable match value to trigger an interrupt.
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*
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* FreeRTOS tick timer appears to come from XTensa core tick timer0,
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* not either of these. FRC2 is used in the FreeRTOS SDK however. It
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* is set to free-run, interrupting periodically via updates to the
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* ALARM register. sdk_ets_timer_init configures FRC2 and assigns FRC2
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* interrupt handler at sdk_vApplicationTickHook+0x68
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*/
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struct TIMER_REGS { // FRC1 FRC2
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uint32_t volatile LOAD; // 0x00 0x20
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uint32_t volatile COUNT; // 0x04 0x24
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uint32_t volatile CTRL; // 0x08 0x28
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uint32_t volatile STATUS; // 0x0c 0x2c
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uint32_t volatile ALARM; // 0x30
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};
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_Static_assert(sizeof(struct TIMER_REGS) == 0x14, "TIMER_REGS is the wrong size");
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#define TIMER_FRC1_MAX_LOAD 0x7fffff
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/* Details for LOAD registers */
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/* Behavior for FRC1:
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*
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* When TIMER_CTRL_RELOAD is cleared in TIMER(0).CTRL, FRC1 will
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* reload to its max value once underflowed (unless the load
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* value is rewritten in the interrupt handler.)
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*
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* When TIMER_CTRL_RELOAD is set in TIMER(0).CTRL, FRC1 will reload
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* from the load register value once underflowed.
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*
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* Behavior for FRC2:
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*
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* If TIMER_CTRL_RELOAD is cleared in TIMER(1).CTRL, writing to
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* this register will update the FRC2 COUNT value.
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*
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* If TIMER_CTRL_RELOAD is set in TIMER(1).CTRL, the behaviour
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* appears to be the same except that writing 0 to the load register
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* both sets the COUNT register to 0 and disables the timer, even if
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* the TIMER_CTRL_RUN bit is set.
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*
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* Offsets 0x34, 0x38, 0x3c all seem to read back the LOAD_REG value
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* also (but have no known function.)
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*/
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/* Details for CTRL registers */
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/* Observed behaviour is like this:
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*
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* * When TIMER_CTRL_INT_HOLD is set, the interrupt status bit
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* TIMER_CTRL_INT_STATUS remains set when the timer interrupt
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* triggers, unless manually cleared by writing 0 to
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* TIMER(x).STATUS. While the interrupt status bit stays set
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* the timer will continue to run normally, but the interrupt
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* (INUM_TIMER_FRC1 or INUM_TIMER_FRC2) won't trigger again.
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*
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* * When TIMER_CTRL_INT_HOLD is cleared (default), there's no need to
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* manually write to TIMER(x).STATUS. The interrupt status bit
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* TIMER_CTRL_INT_STATUS automatically clears after the interrupt
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* triggers, and the interrupt handler will run again
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* automatically.
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*/
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/* The values for TIMER_CTRL_CLKDIV control how many CPU clock cycles amount to
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* one timer clock cycle. For valid values, see the timer_clkdiv_t enum below.
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*/
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/* TIMER_CTRL_INT_STATUS gets set when interrupt fires, and cleared on a write
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* to TIMER(x).STATUS (or cleared automatically if TIMER_CTRL_INT_HOLD is not
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* set).
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*/
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#define TIMER_CTRL_INT_HOLD BIT(0)
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#define TIMER_CTRL_CLKDIV_M 0x00000003
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#define TIMER_CTRL_CLKDIV_S 2
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#define TIMER_CTRL_RELOAD BIT(6)
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#define TIMER_CTRL_RUN BIT(7)
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#define TIMER_CTRL_INT_STATUS BIT(8)
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typedef enum {
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TIMER_CLKDIV_1 = 0,
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TIMER_CLKDIV_16 = 1,
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TIMER_CLKDIV_256 = 2,
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} timer_clkdiv_t;
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/* Details for STATUS registers */
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/* Reading this register always returns the value in
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* TIMER(x).LOAD
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*
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* Writing zero to this register clears the FRC1
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* interrupt status.
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*/
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/* Details for FRC2.ALARM register */
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/* Interrupt match value for FRC2. When COUNT == ALARM,
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the interrupt fires.
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif // DOXYGEN
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#endif /* TIMER_REGS_H */
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