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01b3484ffb
SAML21 provides 2/4/8 kiB of Low Power SRAM that is retained in backup mode. This adds definitions to make that memory availiable to RIOT.
93 lines
3.6 KiB
C
93 lines
3.6 KiB
C
/*
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* Copyright (C) 2015-2016 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_saml21
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* @brief CPU specific definitions for internal peripheral handling
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief The Low Power SRAM is not retained during deep sleep.
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*/
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#define CPU_BACKUP_RAM_NOT_RETAINED (1)
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/**
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* @brief Mapping of pins to EXTI lines, -1 means not EXTI possible
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*/
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#if defined(CPU_MODEL_SAML21E18A) || defined(CPU_MODEL_SAML21E18B) || \
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defined(CPU_MODEL_SAML21E17A) || defined(CPU_MODEL_SAML21E17B) || \
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defined(CPU_MODEL_SAML21E16A) || defined(CPU_MODEL_SAML21E16B) || \
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defined(CPU_MODEL_SAML21E15A) || defined(CPU_MODEL_SAML21E15B)
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static const int8_t exti_config[1][32] = {
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{ 0, 1, 2, 3, 4, 5, 6, 7, -1, 9, 10, 11, -1, -1, 14, 15,
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0, 1, 2, 3, -1, -1, 6, 7, 12, 13, -1, 15, -1, -1, 10, 11},
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};
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#else /* CPU_MODEL_SAML21E */
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static const int8_t exti_config[2][32] = {
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#if defined(CPU_MODEL_SAML21G18A) || defined(CPU_MODEL_SAML21G18B) || \
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defined(CPU_MODEL_SAML21G17A) || defined(CPU_MODEL_SAML21G17B) || \
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defined(CPU_MODEL_SAML21G16A) || defined(CPU_MODEL_SAML21G16B)
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{ 0, 1, 2, 3, 4, 5, 6, 7, -1, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 12, 13, -1, 15, -1, -1, 10, 11},
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{-1, -1, 2, 3, -1, -1, -1, -1, 8, 9, 10, 11, -1, -1, -1, -1,
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-1, -1, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, -1, -1, -1, -1},
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#elif defined(CPU_MODEL_SAML21J18A) || defined(CPU_MODEL_SAML21J18B) || \
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defined(CPU_MODEL_SAML21J17A) || defined(CPU_MODEL_SAML21J17B) || \
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defined(CPU_MODEL_SAML21J16A) || defined(CPU_MODEL_SAML21J16B)
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{ 0, 1, 2, 3, 4, 5, 6, 7, -1, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, 5, 6, 7, 12, 13, -1, 15, -1, -1, 10, 11},
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{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
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0, 1, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, -1, -1, 14, 15},
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#elif defined(CPU_MODEL_SAMR30G18A) || defined(CPU_MODEL_SAMR34J18B)
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{ 0, 1, -1, -1, 4, 5, 6, 7, -1, 9, 10, 11, 12, 13, 14, 15,
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0, 1, 2, 3, 4, -1, 6, 7, 12, 13, -1, 15, 8, -1, 10, 11},
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{ 0, -1, 2, 3, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 15,
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0, 1, -1, -1, -1, -1, 6, 7, -1, -1, -1, -1, -1, -1, 14, 15},
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#elif defined(CPU_MODEL_SAMR30E18A)
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{-1, -1, -1, -1, -1, -1, 6, 7, -1, 9, 10, 11, -1, -1, 14, 15,
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0, 1, 2, 3, 4, -1, -1, -1, 12, 13, -1, 15, 8, -1, 10, 11},
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{ 0, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 15,
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0, 1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, 14, 15},
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#else
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#error Please define a proper CPU_MODEL.
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#endif
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};
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#endif /* CPU_MODEL_SAML21E */
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#define HAVE_ADC_RES_T
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typedef enum {
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ADC_RES_6BIT = 0xff, /**< not supported */
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ADC_RES_8BIT = ADC_CTRLC_RESSEL_8BIT, /**< ADC resolution: 8 bit */
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ADC_RES_10BIT = ADC_CTRLC_RESSEL_10BIT, /**< ADC resolution: 10 bit */
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ADC_RES_12BIT = ADC_CTRLC_RESSEL_12BIT, /**< ADC resolution: 12 bit */
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ADC_RES_14BIT = 0xfe, /**< not supported */
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ADC_RES_16BIT = 0xfd /**< not supported */
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} adc_res_t;
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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