/* * Copyright (C) 2019 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_i-nucleo-lrwan1 * @{ * * @file * @brief Peripheral MCU configuration for the ST I-NUCLEO-LRWAN1 board * * @author Alexandre Abadie */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE #define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" #include "clk_conf.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim2.h" #ifdef __cplusplus extern "C" { #endif /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = LPUART1, .rcc_mask = RCC_APB1ENR_LPUART1EN, .rx_pin = GPIO_PIN(PORT_B, 11), .tx_pin = GPIO_PIN(PORT_B, 10), .rx_af = GPIO_AF4, .tx_af = GPIO_AF4, .bus = APB1, .irqn = LPUART1_IRQn, .type = STM32_LPUART, .clk_src = 0, /* Use APB clock */ }, }; #define UART_0_ISR (isr_rng_lpuart1) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ /** * @name SPI configuration * @{ */ static const spi_conf_t spi_config[] = { { .dev = SPI1, /* connected to SX1272 */ .mosi_pin = GPIO_PIN(PORT_A, 12), .miso_pin = GPIO_PIN(PORT_B, 4), .sclk_pin = GPIO_PIN(PORT_B, 3), .cs_pin = GPIO_PIN(PORT_A, 15), .mosi_af = GPIO_AF0, .miso_af = GPIO_AF0, .sclk_af = GPIO_AF0, .cs_af = GPIO_AF0, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2, }, }; #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ /** * @name I2C configuration * @{ */ static const i2c_conf_t i2c_config[] = { { .dev = I2C1, .speed = I2C_SPEED_NORMAL, .scl_pin = GPIO_PIN(PORT_B, 6), .sda_pin = GPIO_PIN(PORT_B, 7), .scl_af = GPIO_AF1, .sda_af = GPIO_AF1, .bus = APB1, .rcc_mask = RCC_APB1ENR_I2C1EN, .irqn = I2C1_IRQn } }; #define I2C_0_ISR isr_i2c1 #define I2C_NUMOF ARRAY_SIZE(i2c_config) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */