/* * Copyright (C) 2020 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_nucleo-g474re * @{ * * @file * @brief Peripheral MCU configuration for the nucleo-g474re board * * @author Alexandre Abadie */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #include "g4/cfg_clock_default.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_rtt_default.h" #include "cfg_timer_tim5.h" #ifdef __cplusplus extern "C" { #endif /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = LPUART1, .rcc_mask = RCC_APB1ENR2_LPUART1EN, .rx_pin = GPIO_PIN(PORT_A, 3), .tx_pin = GPIO_PIN(PORT_A, 2), .rx_af = GPIO_AF12, .tx_af = GPIO_AF12, .bus = APB12, .irqn = LPUART1_IRQn, .type = STM32_LPUART, .clk_src = 0, /* Use APB clock */ }, { /* Connected to Arduino D0/D1 */ .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_C, 5), .tx_pin = GPIO_PIN(PORT_C, 4), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB2, .irqn = USART1_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ }, }; #define UART_0_ISR (isr_lpuart1) #define UART_1_ISR (isr_usart1) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ /** * @name SPI configuration * * @note The spi_divtable is auto-generated from * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` * @{ */ static const uint8_t spi_divtable[2][5] = { { /* for APB1 @ 80000000Hz */ 7, /* -> 312500Hz */ 7, /* -> 312500Hz */ 5, /* -> 1250000Hz */ 3, /* -> 5000000Hz */ 2 /* -> 10000000Hz */ }, { /* for APB2 @ 80000000Hz */ 7, /* -> 312500Hz */ 7, /* -> 312500Hz */ 5, /* -> 1250000Hz */ 3, /* -> 5000000Hz */ 2 /* -> 10000000Hz */ } }; static const spi_conf_t spi_config[] = { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_A, 7), /* Arduino D11 */ .miso_pin = GPIO_PIN(PORT_A, 6), /* Arduino D12 */ .sclk_pin = GPIO_PIN(PORT_A, 5), /* Arduino D13 */ .cs_pin = GPIO_UNDEF, .mosi_af = GPIO_AF5, .miso_af = GPIO_AF5, .sclk_af = GPIO_AF5, .cs_af = GPIO_AF5, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2, }, }; #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */