/* * Copyright (C) 2014 Freie Universität Berlin * * This file is subject to the terms and conditions of the GNU Lesser General * Public License v2.1. See the file LICENSE in the top level directory for more * details. */ /** * @ingroup boards_spark-core * @{ * * @file * @brief Peripheral MCU configuration for the spark-core board * * @author Christian Mehlis */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #include "f1f3/cfg_clock_default.h" #ifdef __cplusplus extern "C" { #endif /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM2, .max = 0x0000ffff, .rcc_mask = RCC_APB1ENR_TIM2EN, .bus = APB1, .irqn = TIM2_IRQn }, { .dev = TIM3, .max = 0x0000ffff, .rcc_mask = RCC_APB1ENR_TIM3EN, .bus = APB1, .irqn = TIM3_IRQn } }; #define TIMER_0_ISR isr_tim2 #define TIMER_1_ISR isr_tim3 #define TIMER_NUMOF ARRAY_SIZE(timer_config) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART2, .rcc_mask = RCC_APB1ENR_USART2EN, .rx_pin = GPIO_PIN(PORT_A, 3), .tx_pin = GPIO_PIN(PORT_A, 2), .bus = APB1, .irqn = USART2_IRQn } }; #define UART_0_ISR (isr_usart2) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ /** * @name SPI configuration * @{ */ static const spi_conf_t spi_config[] = { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_B, 17), .miso_pin = GPIO_PIN(PORT_B, 16), .sclk_pin = GPIO_PIN(PORT_B, 15), .cs_pin = GPIO_UNDEF, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2 } }; #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ #ifdef __cplusplus } /* end extern "C" */ #endif #endif /* PERIPH_CONF_H */ /** @} */