# Copyright (c) 2020 Inria # # This file is subject to the terms and conditions of the GNU Lesser # General Public License v2.1. See the file LICENSE in the top level # directory for more details. # config CLOCK_HAS_NO_MCO_PRE bool help Indicates that the CPU has no MCO prescaler menu "STM32 clock configuration" depends on !CPU_FAM_F2 && !CPU_FAM_F4 && !CPU_FAM_F7 choice bool "Clock source selection" default USE_CLOCK_PLL config USE_CLOCK_PLL bool "PLL" config USE_CLOCK_MSI bool "Use direct multi-speed frequency internal oscillator (MSI)" depends on CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config USE_CLOCK_HSE bool "Direct High frequency external oscillator (HSE)" depends on BOARD_HAS_HSE config USE_CLOCK_HSI bool "Direct High frequency internal oscillator (HSI16)" endchoice if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB choice bool "Source clock for PLL" if USE_CLOCK_PLL default CLOCK_PLL_SRC_HSE if BOARD_HAS_HSE default CLOCK_PLL_SRC_MSI config CLOCK_PLL_SRC_MSI bool "Use MSI source clock" config CLOCK_PLL_SRC_HSE bool "Use HSE source clock" depends on BOARD_HAS_HSE config CLOCK_PLL_SRC_HSI bool "Use HSI16 source clock" endchoice endif # CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CUSTOM_PLL_PARAMS bool "Configure PLL parameters" depends on USE_CLOCK_PLL if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_PLL_M int "M: PLLIN division factor" if CUSTOM_PLL_PARAMS default 1 if CPU_FAM_G0 default 6 if CPU_FAM_G4 && BOARD_HAS_HSE default 4 if CPU_FAM_G4 default 6 if (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB) && CLOCK_PLL_SRC_MSI default 4 if CPU_FAM_WB && CLOCK_PLL_SRC_HSE default 2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB range 1 8 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB range 1 16 if CPU_FAM_G4 config CLOCK_PLL_N int "N: PLLIN multiply factor" if CUSTOM_PLL_PARAMS default 16 if CPU_FAM_WB default 30 if CPU_LINE_STM32L4A6XX || CPU_LINE_STM32L4P5XX || CPU_LINE_STM32L4Q5XX || CPU_LINE_STM32L4R5XX || CPU_LINE_STM32L4R7XX || CPU_LINE_STM32L4R9XX || CPU_LINE_STM32L4S5XX || CPU_LINE_STM32L4S7XX || CPU_LINE_STM32L4S9XX default 27 if CPU_FAM_L5 default 20 if CPU_FAM_G0 || CPU_FAM_L4 default 85 if CPU_FAM_G4 range 8 86 if CPU_FAM_G0 || CPU_FAM_L4 || CPU_FAM_L5 range 8 127 if CPU_FAM_G4 range 6 127 if CPU_FAM_WB if CPU_FAM_G0 || CPU_FAM_WB config CLOCK_PLL_R int "Q: VCO division factor" if CUSTOM_PLL_PARAMS default 2 if CPU_FAM_WB default 6 if BOARD_HAS_HSE default 5 range 2 8 endif # CPU_FAM_G0 || CPU_FAM_WB if CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 choice bool "R: Main PLL division factor for PLL 'R' clock (system clock)" if CUSTOM_PLL_PARAMS default PLL_R_DIV_2 config PLL_R_DIV_2 bool "Divide by 2" config PLL_R_DIV_4 bool "Divide by 4" config PLL_R_DIV_6 bool "Divide by 6" config PLL_R_DIV_8 bool "Divide by 8" endchoice config CLOCK_PLL_R int default 2 if PLL_R_DIV_2 default 4 if PLL_R_DIV_4 default 6 if PLL_R_DIV_6 default 8 if PLL_R_DIV_8 endif # CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 endif # CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 config CLOCK_PLL_PREDIV int "PLLIN division factor" if CUSTOM_PLL_PARAMS && !CPU_LINE_STM32F031X6 && !CPU_LINE_STM32F042X6 && !CPU_LINE_STM32F303X8 default 2 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 || CPU_LINE_STM32F303X8 default 1 range 1 16 config CLOCK_PLL_MUL int "PLLIN multiply factor" if CUSTOM_PLL_PARAMS default 16 if CPU_LINE_STM32F303X8 default 12 if CPU_LINE_STM32F031X6 || CPU_LINE_STM32F042X6 default 9 if CPU_FAM_F1 || CPU_FAM_F3 default 6 if CPU_FAM_F0 range 2 16 endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_PLL_DIV int "Main PLL division factor" if CUSTOM_PLL_PARAMS default 2 range 2 4 choice bool "Main PLL multiply factor" if CUSTOM_PLL_PARAMS default PLL_MUL_4 config PLL_MUL_3 bool "Multiply by 3" config PLL_MUL_4 bool "Multiply by 4" config PLL_MUL_6 bool "Multiply by 6" config PLL_MUL_8 bool "Multiply by 8" config PLL_MUL_12 bool "Multiply by 12" config PLL_MUL_16 bool "Multiply by 16" config PLL_MUL_24 bool "Multiply by 24" config PLL_MUL_32 bool "Multiply by 32" config PLL_MUL_48 bool "Multiply by 48" endchoice config CLOCK_PLL_MUL int default 3 if PLL_MUL_3 default 4 if PLL_MUL_4 default 6 if PLL_MUL_6 default 8 if PLL_MUL_8 default 12 if PLL_MUL_12 default 16 if PLL_MUL_16 default 24 if PLL_MUL_24 default 32 if PLL_MUL_32 default 48 if PLL_MUL_48 endif # CPU_FAM_L0 || CPU_FAM_L1 if CPU_FAM_G0 choice bool "HSISYS division factor" if USE_CLOCK_HSI default CLOCK_HSISYS_DIV_1 config CLOCK_HSISYS_DIV_1 bool "Divide HSISYS by 1" config CLOCK_HSISYS_DIV_2 bool "Divide HSISYS by 2" config CLOCK_HSISYS_DIV_4 bool "Divide HSISYS by 4" config CLOCK_HSISYS_DIV_8 bool "Divide HSISYS by 8" config CLOCK_HSISYS_DIV_16 bool "Divide HSISYS by 16" config CLOCK_HSISYS_DIV_32 bool "Divide HSISYS by 32" config CLOCK_HSISYS_DIV_64 bool "Divide HSISYS by 64" config CLOCK_HSISYS_DIV_128 bool "Divide HSISYS by 128" endchoice config CLOCK_HSISYS_DIV int default 1 if CLOCK_HSISYS_DIV_1 default 2 if CLOCK_HSISYS_DIV_2 default 4 if CLOCK_HSISYS_DIV_4 default 8 if CLOCK_HSISYS_DIV_8 default 16 if CLOCK_HSISYS_DIV_16 default 32 if CLOCK_HSISYS_DIV_32 default 64 if CLOCK_HSISYS_DIV_64 default 128 if CLOCK_HSISYS_DIV_128 endif # CPU_FAM_G0 if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB choice bool "Desired MSI clock frequency" if USE_CLOCK_MSI || (USE_CLOCK_PLL && CLOCK_PLL_SRC_MSI) default CLOCK_MSI_48MHZ if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB default CLOCK_MSI_4MHZ config CLOCK_MSI_65KHZ bool "65.536kHz" if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_MSI_100KHZ bool "100kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_130KHZ bool "131.072kHz" if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_MSI_200KHZ bool "200kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_260KHZ bool "262.144kHz" if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_MSI_400KHZ bool "400kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_520KHZ bool "524.288kHz" if CPU_FAM_L0 || CPU_FAM_L1 config CLOCK_MSI_800KHZ bool "800kHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_1MHZ bool prompt "1MHz" config CLOCK_MSI_2MHZ bool prompt "2MHz" config CLOCK_MSI_4MHZ bool prompt "4MHz" config CLOCK_MSI_8MHZ bool "8MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_16MHZ bool "16MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_24MHZ bool "24MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_32MHZ bool "32MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB config CLOCK_MSI_48MHZ bool "48MHz" if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB endchoice config CLOCK_MSI int default 65536 if CLOCK_MSI_65KHZ default 131072 if CLOCK_MSI_130KHZ default 262144 if CLOCK_MSI_260KHZ default 524288 if CLOCK_MSI_520KHZ default 100000 if CLOCK_MSI_100KHZ default 200000 if CLOCK_MSI_200KHZ default 400000 if CLOCK_MSI_400KHZ default 800000 if CLOCK_MSI_800KHZ default 1000000 if CLOCK_MSI_1MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB) default 1048000 if CLOCK_MSI_1MHZ && (CPU_FAM_L0 || CPU_FAM_L1) default 2000000 if CLOCK_MSI_2MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB) default 2097000 if CLOCK_MSI_2MHZ && (CPU_FAM_L0 || CPU_FAM_L1) default 4000000 if CLOCK_MSI_4MHZ && (CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB) default 4194000 if CLOCK_MSI_4MHZ && (CPU_FAM_L0 || CPU_FAM_L1) default 8000000 if CLOCK_MSI_8MHZ default 16000000 if CLOCK_MSI_16MHZ default 24000000 if CLOCK_MSI_24MHZ default 32000000 if CLOCK_MSI_32MHZ default 48000000 if CLOCK_MSI_48MHZ endif # CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB choice bool "APB1 prescaler (division factor of HCLK to produce PCLK1)" default CLOCK_APB1_DIV_4 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 default CLOCK_APB1_DIV_1 config CLOCK_APB1_DIV_1 bool "Divide HCLK by 1" config CLOCK_APB1_DIV_2 bool "Divide HCLK by 2" config CLOCK_APB1_DIV_4 bool "Divide HCLK by 4" config CLOCK_APB1_DIV_8 bool "Divide HCLK by 8" config CLOCK_APB1_DIV_16 bool "Divide HCLK by 16" endchoice config CLOCK_APB1_DIV int default 1 if CLOCK_APB1_DIV_1 default 2 if CLOCK_APB1_DIV_2 default 4 if CLOCK_APB1_DIV_4 default 8 if CLOCK_APB1_DIV_8 default 16 if CLOCK_APB1_DIV_16 choice bool "APB2 prescaler (division factor of HCLK to produce PCLK2)" depends on !CPU_FAM_G0 && !CPU_FAM_F0 default CLOCK_APB2_DIV_2 if CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_WB default CLOCK_APB2_DIV_1 config CLOCK_APB2_DIV_1 bool "Divide HCLK by 1" config CLOCK_APB2_DIV_2 bool "Divide HCLK by 2" config CLOCK_APB2_DIV_4 bool "Divide HCLK by 4" config CLOCK_APB2_DIV_8 bool "Divide HCLK by 8" config CLOCK_APB2_DIV_16 bool "Divide HCLK by 16" endchoice config CLOCK_APB2_DIV int default 1 if CLOCK_APB2_DIV_1 default 2 if CLOCK_APB2_DIV_2 default 4 if CLOCK_APB2_DIV_4 default 8 if CLOCK_APB2_DIV_8 default 16 if CLOCK_APB2_DIV_16 if CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB config CLOCK_ENABLE_MCO bool "Enable MCU Clock Output (MCO) on PA8" choice bool "MCO source" depends on CLOCK_ENABLE_MCO default CLOCK_MCO_USE_PLLCLK config CLOCK_MCO_USE_PLLCLK bool "Use PLLCLK as MCO source" config CLOCK_MCO_USE_HSE bool "Use HSE as MCO source" config CLOCK_MCO_USE_HSI bool "Use HSI as MCO source" config CLOCK_MCO_USE_LSE bool "Use LSE as MCO source" if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB config CLOCK_MCO_USE_LSI bool "Use LSI as MCO source" if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB config CLOCK_MCO_USE_MSI bool "Use MSI as MCO source" if CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB config CLOCK_MCO_USE_SYSCLK bool "Use SYSCLK as MCO source" endchoice choice bool "MCO prescaler" depends on !CLOCK_HAS_NO_MCO_PRE && CLOCK_ENABLE_MCO default CLOCK_MCO_PRE_1 config CLOCK_MCO_PRE_1 bool "Divide MCO by 1" config CLOCK_MCO_PRE_2 bool "Divide MCO by 2" config CLOCK_MCO_PRE_4 bool "Divide MCO by 4" config CLOCK_MCO_PRE_8 bool "Divide MCO by 8" config CLOCK_MCO_PRE_16 bool "Divide MCO by 16" config CLOCK_MCO_PRE_32 bool "Divide MCO by 32" if !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB config CLOCK_MCO_PRE_64 bool "Divide MCO by 64" if !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB config CLOCK_MCO_PRE_128 bool "Divide MCO by 128" if !CPU_FAM_G4 && !CPU_FAM_L0 && !CPU_FAM_L1 && !CPU_FAM_L4 && !CPU_FAM_WB endchoice config CLOCK_MCO_PRE int default 2 if CLOCK_MCO_PRE_2 default 4 if CLOCK_MCO_PRE_4 default 8 if CLOCK_MCO_PRE_8 default 16 if CLOCK_MCO_PRE_16 default 32 if CLOCK_MCO_PRE_32 default 64 if CLOCK_MCO_PRE_64 default 128 if CLOCK_MCO_PRE_128 default 1 endif # CPU_FAM_F0 || CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_L4 || CPU_FAM_WB endmenu