/* * Copyright (C) 2017 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_b-l475e-iot01a * @{ * * @file * @brief Peripheral MCU configuration for the B-L475E-IOT01A board * * @author Alexandre Abadie */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #include "cfg_rtt_default.h" #ifdef __cplusplus extern "C" { #endif /** * @name Clock system configuration * @{ */ /* 0: no external high speed crystal available * else: actual crystal frequency [in Hz] */ #define CLOCK_HSE (0) /* 0: no external low speed crystal available, * 1: external crystal available (always 32.768kHz) */ #define CLOCK_LSE (1) /* 0: enable MSI only if HSE isn't available * 1: always enable MSI (e.g. if USB or RNG is used)*/ #define CLOCK_MSI_ENABLE (1) /* 0: disable Hardware auto calibration with LSE * 1: enable Hardware auto calibration with LSE (PLL-mode)*/ #define CLOCK_MSI_LSE_PLL (1) /* give the target core clock (HCLK) frequency [in Hz], maximum: 80MHz */ #define CLOCK_CORECLOCK (80000000U) /* PLL configuration: make sure your values are legit! * * compute by: CORECLOCK = (((PLL_IN / M) * N) / R) * with: * PLL_IN: input clock, HSE or MSI @ 48MHz * M: pre-divider, allowed range: [1:8] * N: multiplier, allowed range: [8:86] * R: post-divider, allowed range: [2,4,6,8] * * Also the following constraints need to be met: * (PLL_IN / M) -> [4MHz:16MHz] * (PLL_IN / M) * N -> [64MHz:344MHz] * CORECLOCK -> 80MHz MAX! */ #define CLOCK_PLL_M (6) #define CLOCK_PLL_N (20) #define CLOCK_PLL_R (2) /* peripheral clock setup */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 #define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 #define CLOCK_APB1 (CLOCK_CORECLOCK / 4) #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 #define CLOCK_APB2 (CLOCK_CORECLOCK / 2) /** @} */ /** * @name DMA streams configuration * @{ */ #ifdef MODULE_PERIPH_DMA static const dma_conf_t dma_config[] = { { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX */ { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */ { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */ { .stream = 10 }, /* DMA2 Channel 3 - UART4_TX */ }; #define DMA_0_ISR isr_dma1_channel2 #define DMA_1_ISR isr_dma1_channel3 #define DMA_2_ISR isr_dma1_channel4 #define DMA_3_ISR isr_dma2_channel3 #define DMA_NUMOF ARRAY_SIZE(dma_config) #endif /** @} */ /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM5, .max = 0xffffffff, .rcc_mask = RCC_APB1ENR1_TIM5EN, .bus = APB1, .irqn = TIM5_IRQn } }; #define TIMER_0_ISR isr_tim5 #define TIMER_NUMOF ARRAY_SIZE(timer_config) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_B, 7), .tx_pin = GPIO_PIN(PORT_B, 6), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB2, .irqn = USART1_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 2, .dma_chan = 2 #endif }, { .dev = UART4, .rcc_mask = RCC_APB1ENR1_UART4EN, .rx_pin = GPIO_PIN(PORT_A, 1), .tx_pin = GPIO_PIN(PORT_A, 0), .rx_af = GPIO_AF8, .tx_af = GPIO_AF8, .bus = APB1, .irqn = UART4_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 3, .dma_chan = 2 #endif } }; #define UART_0_ISR (isr_usart1) #define UART_1_ISR (isr_uart4) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ /** * @name PWM configuration * @{ */ static const pwm_conf_t pwm_config[] = { { .dev = TIM2, .rcc_mask = RCC_APB1ENR1_TIM2EN, .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0}, /* D9 */ { .pin = GPIO_UNDEF, .cc_chan = 0}, { .pin = GPIO_UNDEF, .cc_chan = 0}, { .pin = GPIO_UNDEF, .cc_chan = 0} }, .af = GPIO_AF1, .bus = APB1 } }; #define PWM_NUMOF ARRAY_SIZE(pwm_config) /** @} */ /** * @name SPI configuration * * @note The spi_divtable is auto-generated from * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` * @{ */ static const uint8_t spi_divtable[2][5] = { { /* for APB1 @ 20000000Hz */ 7, /* -> 78125Hz */ 5, /* -> 312500Hz */ 3, /* -> 1250000Hz */ 1, /* -> 5000000Hz */ 0 /* -> 10000000Hz */ }, { /* for APB2 @ 40000000Hz */ 7, /* -> 156250Hz */ 6, /* -> 312500Hz */ 4, /* -> 1250000Hz */ 2, /* -> 5000000Hz */ 1 /* -> 10000000Hz */ } }; static const spi_conf_t spi_config[] = { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_A, 7), .miso_pin = GPIO_PIN(PORT_A, 6), .sclk_pin = GPIO_PIN(PORT_A, 5), .cs_pin = GPIO_UNDEF, .mosi_af = GPIO_AF5, .miso_af = GPIO_AF5, .sclk_af = GPIO_AF5, .cs_af = GPIO_AF5, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2, #ifdef MODULE_PERIPH_DMA .tx_dma = 1, .tx_dma_chan = 1, .rx_dma = 0, .rx_dma_chan = 1, #endif } }; #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ /** * @name I2C configuration * @{ */ static const i2c_conf_t i2c_config[] = { { .dev = I2C1, .speed = I2C_SPEED_NORMAL, .scl_pin = GPIO_PIN(PORT_B, 8), .sda_pin = GPIO_PIN(PORT_B, 9), .scl_af = GPIO_AF4, .sda_af = GPIO_AF4, .bus = APB1, .rcc_mask = RCC_APB1ENR1_I2C1EN, .irqn = I2C1_ER_IRQn, }, { .dev = I2C2, .speed = I2C_SPEED_NORMAL, .scl_pin = GPIO_PIN(PORT_B, 10), .sda_pin = GPIO_PIN(PORT_B, 11), .scl_af = GPIO_AF4, .sda_af = GPIO_AF4, .bus = APB1, .rcc_mask = RCC_APB1ENR1_I2C2EN, .irqn = I2C2_ER_IRQn, }, }; #define I2C_0_ISR isr_i2c1_er #define I2C_1_ISR isr_i2c2_er #define I2C_NUMOF ARRAY_SIZE(i2c_config) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */