/* * Copyright (C) 2017 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @defgroup boards_nucleo-f446ze STM32 Nucleo-F446ZE * @ingroup boards_common_nucleo144 * @brief Support for the STM32 Nucleo-F446ZE * @{ * * @file * @name Peripheral MCU configuration for the nucleo-f446ze board * * @author Alexandre Abadie */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #include "f4/cfg_clock_180_8_1.h" #include "cfg_spi_divtable.h" #ifdef __cplusplus extern "C" { #endif /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM5, .max = 0xffffffff, .rcc_mask = RCC_APB1ENR_TIM5EN, .bus = APB1, .irqn = TIM5_IRQn } }; #define TIMER_0_ISR isr_tim5 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART3, .rcc_mask = RCC_APB1ENR_USART3EN, .rx_pin = GPIO_PIN(PORT_D, 9), .tx_pin = GPIO_PIN(PORT_D, 8), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART3_IRQn, #ifdef UART_USE_DMA .dma_stream = 6, .dma_chan = 4 #endif }, { .dev = USART6, .rcc_mask = RCC_APB2ENR_USART6EN, .rx_pin = GPIO_PIN(PORT_G, 9), .tx_pin = GPIO_PIN(PORT_G, 14), .rx_af = GPIO_AF8, .tx_af = GPIO_AF8, .bus = APB2, .irqn = USART6_IRQn, #ifdef UART_USE_DMA .dma_stream = 5, .dma_chan = 4 #endif }, { .dev = USART2, .rcc_mask = RCC_APB1ENR_USART2EN, .rx_pin = GPIO_PIN(PORT_D, 6), .tx_pin = GPIO_PIN(PORT_D, 5), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART2_IRQn, #ifdef UART_USE_DMA .dma_stream = 4, .dma_chan = 4 #endif }, }; #define UART_0_ISR (isr_usart3) #define UART_0_DMA_ISR (isr_dma1_stream6) #define UART_1_ISR (isr_usart6) #define UART_1_DMA_ISR (isr_dma1_stream5) #define UART_2_ISR (isr_usart2) #define UART_2_DMA_ISR (isr_dma1_stream4) #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) /** @} */ /** * @name PWM configuration * @{ */ static const pwm_conf_t pwm_config[] = { { .dev = TIM1, .rcc_mask = RCC_APB2ENR_TIM1EN, .chan = { { .pin = GPIO_PIN(PORT_E, 9) /* D6 */, .cc_chan = 0}, { .pin = GPIO_PIN(PORT_E, 11) /* D5 */, .cc_chan = 1}, { .pin = GPIO_PIN(PORT_E, 13) /* D3 */, .cc_chan = 2}, { .pin = GPIO_UNDEF, .cc_chan = 0} }, .af = GPIO_AF1, .bus = APB2 }, { .dev = TIM4, .rcc_mask = RCC_APB1ENR_TIM4EN, .chan = { { .pin = GPIO_PIN(PORT_D, 15) /* D9 */, .cc_chan = 3}, { .pin = GPIO_UNDEF, .cc_chan = 0}, { .pin = GPIO_UNDEF, .cc_chan = 0}, { .pin = GPIO_UNDEF, .cc_chan = 0} }, .af = GPIO_AF2, .bus = APB1 }, }; #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) /** @} */ /** * @name SPI configuration * @{ */ static const spi_conf_t spi_config[] = { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_A, 7), .miso_pin = GPIO_PIN(PORT_A, 6), .sclk_pin = GPIO_PIN(PORT_A, 5), .cs_pin = GPIO_UNDEF, .af = GPIO_AF5, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2 } }; #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ /** * @name I2C configuration * @{ */ static const i2c_conf_t i2c_config[] = { { .dev = I2C1, .speed = I2C_SPEED_NORMAL, .scl_pin = GPIO_PIN(PORT_B, 8), .sda_pin = GPIO_PIN(PORT_B, 9), .scl_af = GPIO_AF4, .sda_af = GPIO_AF4, .bus = APB1, .rcc_mask = RCC_APB1ENR_I2C1EN, .clk = CLOCK_APB1, .irqn = I2C1_EV_IRQn } }; #define I2C_0_ISR isr_i2c1_ev #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) /** @} */ /** * @name ADC configuration * @{ */ #define ADC_NUMOF (0) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */