include $(RIOTCPU)/stm32/stm32_info.mk

ifneq (mp1,$(CPU_FAM))
  FEATURES_PROVIDED += bootloader_stm32
  FEATURES_PROVIDED += periph_wdt
endif
FEATURES_PROVIDED += cpu_stm32$(CPU_FAM)
FEATURES_PROVIDED += periph_cpuid
FEATURES_PROVIDED += periph_gpio periph_gpio_irq
FEATURES_PROVIDED += periph_gpio_ll
FEATURES_PROVIDED += periph_gpio_ll_disconnect
FEATURES_PROVIDED += periph_gpio_ll_input_pull_down
FEATURES_PROVIDED += periph_gpio_ll_input_pull_up
FEATURES_PROVIDED += periph_gpio_ll_irq
FEATURES_PROVIDED += periph_gpio_ll_irq_edge_triggered_both
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_low
FEATURES_PROVIDED += periph_gpio_ll_open_drain
FEATURES_PROVIDED += periph_rtt_overflow
FEATURES_PROVIDED += periph_spi_reconfigure
FEATURES_PROVIDED += periph_timer_periodic
FEATURES_PROVIDED += periph_timer_query_freqs
FEATURES_PROVIDED += periph_uart_modecfg
FEATURES_PROVIDED += periph_uart_nonblocking

ifneq (f1,$(CPU_FAM))
  FEATURES_PROVIDED += periph_gpio_ll_open_drain_pull_up
  FEATURES_PROVIDED += periph_gpio_ll_switch_dir
endif

ifneq (,$(filter $(CPU_FAM),c0 f0 f1 f3 g0 g4 l0 l1 l4 l5 u5 wb wl))
  FEATURES_PROVIDED += periph_flashpage
  FEATURES_PROVIDED += periph_flashpage_in_address_space
  FEATURES_PROVIDED += periph_flashpage_pagewise
endif

ifneq (,$(filter $(CPU_FAM),f0 f2 f3 f4 f7 l0 l1 l4 l5 u5 wb wl))
  CPU_MODELS_WITHOUT_RTC_BKPR += stm32f030% stm32f070%
  ifeq (,$(filter $(CPU_MODELS_WITHOUT_RTC_BKPR),$(CPU_MODEL)))
    FEATURES_PROVIDED += periph_rtc_mem
  endif
endif

STM32_WITH_BKPRAM = stm32f205% stm32f207% stm32f215% stm32f217% \
                    stm32f405% stm32f407% stm32f415% stm32f417% \
                    stm32f427% stm32f429% stm32f437% stm32f439% \
                    stm32f446% stm32f469% stm32f479% \
                    stm32f7% \
                    stm32u5%
ifneq (,$(filter $(STM32_WITH_BKPRAM),$(CPU_MODEL)))
  FEATURES_PROVIDED += backup_ram
endif

STM32_WITH_VBAT = stm32f031% stm32f038% stm32f042% stm32f048% \
                  stm32f051% stm32f058% stm32f071% stm32f072% \
                  stm32f078% stm32f091% stm32f098% \
                  stm32f2% \
                  stm32f3% \
                  stm32f4% \
                  stm32f7% \
                  stm32g0% \
                  stm32g4% stm32gbk1cb \
                  stm32l4% \
                  stm32l5% \
                  stm32u5% \
                  stm32wb% \
                  stm32wl%

ifneq (,$(filter $(STM32_WITH_VBAT),$(CPU_MODEL)))
  FEATURES_PROVIDED += periph_vbat
endif

# The f2, f4 and f7 do not support the pagewise api
ifneq (,$(filter $(CPU_FAM),f2 f4 f7))
  FEATURES_PROVIDED += periph_flashpage
endif

ifneq (,$(filter $(CPU_FAM),l0 l1))
  FEATURES_PROVIDED += periph_eeprom
endif

ifeq (f1,$(CPU_FAM))
  FEATURES_CONFLICT += periph_rtc:periph_rtt
  FEATURES_CONFLICT_MSG += "On the STM32F1, the RTC and RTT map to the same hardware peripheral."
  FEATURES_PROVIDED += periph_rtt_set_counter
endif

# Not all F4 and L0 parts implement a RNG.
CPU_MODELS_WITHOUT_HWRNG = stm32f401% stm32f411% stm32f446% stm32l031% stm32l011%
ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l0 l4 l5 u5 wb))
  ifeq (,$(filter $(CPU_MODELS_WITHOUT_HWRNG),$(CPU_MODEL)))
    FEATURES_PROVIDED += periph_hwrng
  endif
endif

ifneq (,$(filter $(CPU_FAM),f2 f4 f7 l4))
  FEATURES_PROVIDED += periph_sdmmc_auto_clk
  FEATURES_PROVIDED += periph_sdmmc_clk
  FEATURES_PROVIDED += periph_sdmmc_hs
  FEATURES_PROVIDED += periph_sdmmc_mmc
endif

ifneq (,$(filter $(CPU_FAM),f2 f4 f7 g4 l1 l4 mp1))
  FEATURES_PROVIDED += cortexm_mpu
endif

# only some stm32f3 have an MPU, stm32l052t8 provides an MPU but support is
# broken for cortex-m0+
STM32_WITH_MPU += stm32f303re stm32f303vc stm32f303ze
ifneq (,$(filter $(CPU_MODEL),$(STM32_WITH_MPU)))
  FEATURES_PROVIDED += cortexm_mpu
endif

include $(RIOTCPU)/cortexm_common/Makefile.features