# Copyright (c) 2020 HAW Hamburg
#               2022 Gunar Schorcht
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.

## Definition of specific features
config HAS_ARCH_ESP32
    bool
    help
        Indicates that the current architecture is any ESP32x SoC architecture.

config HAS_CPU_ESP32
    bool
    help
        Indicates that the current CPU belongs to the ESP32x SoC series.

config HAS_ESP_BLE
    bool
    help
        Indicates that the used ESP32x SoC supports Bluetooth LE.

config HAS_ESP_BLE_ESP32
    bool
    help
        Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
        for the ESP32 variant.

config HAS_ESP_BLE_ESP32C3
    bool
    help
        Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
        for the ESP32-C3 or ESP32-S3 variant.

config HAS_ESP_HW_COUNTER
    bool
    help
        Indicates that the used ESP32x SoC supports HW counters that can be
        used as timers.

config HAS_ESP_RMT
    bool
    help
        Indicates that the ESP32x SoC has a RMT peripheral.

config HAS_ESP_RTC_TIMER_32K
    bool
    help
        Indicates that an external 32.768 kHz crystal is connected to the
        ESP32x Soc on the board.

config HAS_ESP_SPI_RAM
    bool
    help
        Indicates that an external RAM is connected via the SPI interface to
        the ESP32x SoC on the board.

config HAS_ESP_SPI_OCT
    bool
    help
        Indicates that Octal SPI mode is used for Flash and SPI RAM. In this
        case additional GPIOs are used for the SPI interface and cannot be
        used for other purposes.

config CPU
    default "esp32" if HAS_CPU_ESP32

config CPU_CORE_XTENSA_LX6
    bool
    select CPU_ARCH_XTENSA
    help
        CPU core of the ESP32x SoC is a Xtensa LX6.

config CPU_CORE_XTENSA_LX7
    bool
    select CPU_ARCH_XTENSA
    help
        CPU core of the ESP32x SoC is a Xtensa LX7.

config CPU_CORE_RV32IMC
    bool
    select CPU_ARCH_RISCV
    help
        CPU core of the ESP32x SoC is a RISC-V core.

config CPU_CORE
    default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
    default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
    default "rv32imc" if CPU_CORE_RV32IMC

rsource "Kconfig.esp32"
rsource "Kconfig.esp32c3"
rsource "Kconfig.esp32s3"
rsource "Kconfig.esp32s2"

source "$(RIOTCPU)/esp_common/Kconfig"