/* * Copyright (C) 2017 Freie Universität Berlin * 2017 Inria * 2017 HAW-Hamburg * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_nucleo-l476rg * @{ * * @file * @brief Peripheral MCU configuration for the nucleo-l476rg board * * @author Hauke Petersen * @author Alexandre Abadie * @author Michel Rottleuthner */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H /* Add specific clock configuration (HSE, LSE) for this board here */ #ifndef CONFIG_BOARD_HAS_LSE #define CONFIG_BOARD_HAS_LSE 1 #endif #include "periph_cpu.h" #include "clk_conf.h" #include "cfg_i2c1_pb8_pb9.h" #include "cfg_rtt_default.h" #ifdef __cplusplus extern "C" { #endif /** * @name DMA streams configuration * @{ */ static const dma_conf_t dma_config[] = { { .stream = 1 }, /* DMA1 Channel 2 - SPI1_RX | USART3_TX */ { .stream = 2 }, /* DMA1 Channel 3 - SPI1_TX */ { .stream = 3 }, /* DMA1 Channel 4 - USART1_TX */ { .stream = 6 }, /* DMA1 Channel 7 - USART2_TX */ }; #define DMA_0_ISR isr_dma1_channel2 #define DMA_1_ISR isr_dma1_channel3 #define DMA_2_ISR isr_dma1_channel4 #define DMA_3_ISR isr_dma1_channel7 #define DMA_NUMOF ARRAY_SIZE(dma_config) /** @} */ /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM5, .max = 0xffffffff, .rcc_mask = RCC_APB1ENR1_TIM5EN, .bus = APB1, .irqn = TIM5_IRQn } }; #define TIMER_0_ISR isr_tim5 #define TIMER_NUMOF ARRAY_SIZE(timer_config) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART2, .rcc_mask = RCC_APB1ENR1_USART2EN, .rx_pin = GPIO_PIN(PORT_A, 3), .tx_pin = GPIO_PIN(PORT_A, 2), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART2_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 3, .dma_chan = 2 #endif }, { .dev = USART3, .rcc_mask = RCC_APB1ENR1_USART3EN, .rx_pin = GPIO_PIN(PORT_C, 11), .tx_pin = GPIO_PIN(PORT_C, 10), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB1, .irqn = USART3_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 0, .dma_chan = 2 #endif }, { .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_A, 10), .tx_pin = GPIO_PIN(PORT_A, 9), .rx_af = GPIO_AF7, .tx_af = GPIO_AF7, .bus = APB2, .irqn = USART1_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 2, .dma_chan = 2 #endif } }; #define UART_0_ISR (isr_usart2) #define UART_1_ISR (isr_usart3) #define UART_2_ISR (isr_usart1) #define UART_NUMOF ARRAY_SIZE(uart_config) /** @} */ /** * @name PWM configuration * @{ */ static const pwm_conf_t pwm_config[] = { { .dev = TIM2, .rcc_mask = RCC_APB1ENR1_TIM2EN, .chan = { { .pin = GPIO_PIN(PORT_A, 15), .cc_chan = 0}, { .pin = GPIO_PIN(PORT_B, 3), .cc_chan = 1}, { .pin = GPIO_PIN(PORT_B, 10), .cc_chan = 2}, { .pin = GPIO_PIN(PORT_B, 11), .cc_chan = 3} }, .af = GPIO_AF1, .bus = APB1 }, { .dev = TIM3, .rcc_mask = RCC_APB1ENR1_TIM3EN, .chan = { { .pin = GPIO_PIN(PORT_B, 4), .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 } }, .af = GPIO_AF2, .bus = APB1 }, { .dev = TIM8, .rcc_mask = RCC_APB2ENR_TIM8EN, .chan = { { .pin = GPIO_PIN(PORT_C, 6), .cc_chan = 0}, { .pin = GPIO_PIN(PORT_C, 7), .cc_chan = 1}, { .pin = GPIO_PIN(PORT_C, 8), .cc_chan = 2}, { .pin = GPIO_PIN(PORT_C, 9), .cc_chan = 3} }, .af = GPIO_AF3, .bus = APB2 } }; #define PWM_NUMOF ARRAY_SIZE(pwm_config) /** @} */ /** * @name SPI configuration * @{ */ static const spi_conf_t spi_config[] = { { .dev = SPI1, .mosi_pin = GPIO_PIN(PORT_A, 7), .miso_pin = GPIO_PIN(PORT_A, 6), .sclk_pin = GPIO_PIN(PORT_A, 5), .cs_pin = SPI_CS_UNDEF, .mosi_af = GPIO_AF5, .miso_af = GPIO_AF5, .sclk_af = GPIO_AF5, .cs_af = GPIO_AF5, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2, #ifdef MODULE_PERIPH_DMA .tx_dma = 1, .tx_dma_chan = 1, .rx_dma = 0, .rx_dma_chan = 1, #endif } }; #define SPI_NUMOF ARRAY_SIZE(spi_config) /** @} */ /** * @brief ADC configuration * * Note that we do not configure all ADC channels, * and not in the STM32L476RG order. Instead, we * just define 6 ADC channels, for the Nucleo * Arduino header pins A0-A5 and the internal VBAT channel. * * To find appropriate device and channel find in the * board manual, table showing pin assignments and * information about ADC - a text similar to ADC[X]_IN[Y], * where: * [X] - describes used device - indexed from 0, * for example ADC1_IN10 is device 0, * [Y] - describes used channel - indexed from 1, * for example ADC1_IN10 is channel 10 * * For Nucleo-L476RG this information is in board manual, * Table 23, page 52. * * VBAT is connected ADC1_IN18 or ADC3_IN18 and a voltage divider * is used, so that only 1/3 of the actual VBAT is measured. This * allows for a supply voltage higher than the reference voltage. * * For Nucleo-L476RG more information is provided in MCU datasheet, * in section 3.15.3 - Vbat battery voltage monitoring, page 42. * @{ */ static const adc_conf_t adc_config[] = { {GPIO_PIN(PORT_A, 0), 0, 5}, /*< ADC12_IN5 */ {GPIO_PIN(PORT_A, 1), 0, 6}, /*< ADC12_IN6 */ {GPIO_PIN(PORT_A, 4), 1, 9}, /*< ADC12_IN9 */ {GPIO_PIN(PORT_B, 0), 1, 15}, /*< ADC12_IN15 */ {GPIO_PIN(PORT_C, 1), 2, 2}, /*< ADC123_IN2 */ {GPIO_PIN(PORT_C, 0), 2, 1}, /*< ADC123_IN1 */ {GPIO_UNDEF, 0, 18}, /* VBAT */ }; #define VBAT_ADC ADC_LINE(6) /**< VBAT ADC line */ #define ADC_NUMOF ARRAY_SIZE(adc_config) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */