/* * Copyright (C) 2017 Inria * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_b-l072z-lrwan1 * @{ * * @file * @brief Peripheral MCU configuration for the ST B-L072Z-LRWAN1 board * * @author Alexandre Abadie */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #ifdef __cplusplus extern "C" { #endif /** * @name Clock system configuration * @{ */ #define CLOCK_HSI (16000000U) /* internal oscillator */ #define CLOCK_CORECLOCK (32000000U) /* desired core clock frequency */ /* configuration of PLL prescaler and multiply values */ /* CORECLOCK := HSI / CLOCK_PLL_DIV * CLOCK_PLL_MUL */ #define CLOCK_PLL_DIV RCC_CFGR_PLLDIV2 #define CLOCK_PLL_MUL RCC_CFGR_PLLMUL4 /* configuration of peripheral bus clock prescalers */ #define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1 /* AHB clock -> 32MHz */ #define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV1 /* APB2 clock -> 32MHz */ #define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV1 /* APB1 clock -> 32MHz */ /* configuration of flash access cycles */ #define CLOCK_FLASH_LATENCY FLASH_ACR_LATENCY /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ #define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1) #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) /** @} */ /** * @name DMA streams configuration * @{ */ #ifdef MODULE_PERIPH_DMA static const dma_conf_t dma_config[] = { { .stream = 1 }, /* channel 2 */ { .stream = 2 }, /* channel 3 */ { .stream = 3 }, /* channel 4 */ { .stream = 4 }, /* channel 5 */ { .stream = 5 }, /* channel 6 */ }; #define DMA_SHARED_ISR_0 isr_dma1_channel2_3 #define DMA_SHARED_ISR_0_STREAMS { 0, 1 } /* Indexes 0 and 1 of dma_config share the same isr */ #define DMA_SHARED_ISR_1 isr_dma1_channel4_5_6_7 #define DMA_SHARED_ISR_1_STREAMS { 2, 3, 4 } /* Indexes 2, 3 and 4 of dma_config share the same isr */ #define DMA_NUMOF (sizeof(dma_config) / sizeof(dma_config[0])) #endif /** @} */ /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM2, .max = 0x0000ffff, .rcc_mask = RCC_APB1ENR_TIM2EN, .bus = APB1, .irqn = TIM2_IRQn } }; #define TIMER_0_ISR isr_tim2 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART2, .rcc_mask = RCC_APB1ENR_USART2EN, .rx_pin = GPIO_PIN(PORT_A, 3), .tx_pin = GPIO_PIN(PORT_A, 2), .rx_af = GPIO_AF4, .tx_af = GPIO_AF4, .bus = APB1, .irqn = USART2_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 2, .dma_chan = 4, #endif }, { .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_A, 10), .tx_pin = GPIO_PIN(PORT_A, 9), .rx_af = GPIO_AF4, .tx_af = GPIO_AF4, .bus = APB2, .irqn = USART1_IRQn, .type = STM32_USART, .clk_src = 0, /* Use APB clock */ #ifdef MODULE_PERIPH_DMA .dma = 0, .dma_chan = 3, #endif }, }; #define UART_0_ISR (isr_usart2) #define UART_1_ISR (isr_usart1) #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) /** @} */ /** * @name SPI configuration * * @note The spi_divtable is auto-generated from * `cpu/stm32_common/dist/spi_divtable/spi_divtable.c` * @{ */ static const uint8_t spi_divtable[2][5] = { { /* for APB1 @ 32000000Hz */ 7, /* -> 125000Hz */ 5, /* -> 500000Hz */ 4, /* -> 1000000Hz */ 2, /* -> 4000000Hz */ 1 /* -> 8000000Hz */ }, { /* for APB2 @ 32000000Hz */ 7, /* -> 125000Hz */ 5, /* -> 500000Hz */ 4, /* -> 1000000Hz */ 2, /* -> 4000000Hz */ 1 /* -> 8000000Hz */ } }; static const spi_conf_t spi_config[] = { { .dev = SPI2, .mosi_pin = GPIO_PIN(PORT_B, 15), .miso_pin = GPIO_PIN(PORT_B, 14), .sclk_pin = GPIO_PIN(PORT_B, 13), .cs_pin = GPIO_UNDEF, .af = GPIO_AF0, .rccmask = RCC_APB1ENR_SPI2EN, .apbbus = APB1, #ifdef MODULE_PERIPH_DMA .tx_dma = 3, .tx_dma_chan = 2, .rx_dma = 2, .rx_dma_chan = 2, #endif }, { .dev = SPI1, /* connected to SX1276 */ .mosi_pin = GPIO_PIN(PORT_A, 7), .miso_pin = GPIO_PIN(PORT_A, 6), .sclk_pin = GPIO_PIN(PORT_B, 3), .cs_pin = GPIO_UNDEF, .af = GPIO_AF0, .rccmask = RCC_APB2ENR_SPI1EN, .apbbus = APB2, #ifdef MODULE_PERIPH_DMA .tx_dma = 1, .tx_dma_chan = 1, .rx_dma = 0, .rx_dma_chan = 1, #endif }, }; #define SPI_NUMOF (sizeof(spi_config) / sizeof(spi_config[0])) /** @} */ /** * @name I2C configuration * @{ */ static const i2c_conf_t i2c_config[] = { { .dev = I2C1, .speed = I2C_SPEED_NORMAL, .scl_pin = GPIO_PIN(PORT_B, 8), .sda_pin = GPIO_PIN(PORT_B, 9), .scl_af = GPIO_AF4, .sda_af = GPIO_AF4, .bus = APB1, .rcc_mask = RCC_APB1ENR_I2C1EN, .irqn = I2C1_IRQn } }; #define I2C_0_ISR isr_i2c1 #define I2C_NUMOF (sizeof(i2c_config) / sizeof(i2c_config[0])) /** @} */ /** * @name RTT configuration * * On the STM32Lx platforms, we always utilize the LPTIM1. * @{ */ #define RTT_NUMOF (1) #define RTT_FREQUENCY (1024U) /* 32768 / 2^n */ #define RTT_MAX_VALUE (0x0000ffff) /* 16-bit timer */ /** @} */ /** * @name RTC configuration * @{ */ #define RTC_NUMOF (1U) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */