# Copyright (c) 2022 HAW Hamburg
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#

if CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1

choice
bool "Main PLL division factor (PLLP) for main system clock" if CUSTOM_PLL_PARAMS
default PLL_P_DIV_4 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
default PLL_P_DIV_2

config PLL_P_DIV_2
    bool "Divide by 2"

config PLL_P_DIV_4
    bool "Divide by 4"

config PLL_P_DIV_6
    bool "Divide by 6"

config PLL_P_DIV_8
    bool "Divide by 8"

endchoice

config CLOCK_PLL_P
    int
    default 3 if CPU_FAM_MP1
    default 2 if PLL_P_DIV_2
    default 4 if PLL_P_DIV_4
    default 6 if PLL_P_DIV_6
    default 8 if PLL_P_DIV_8

config CLOCK_PLL_Q
    int "Main PLL division factor (PLLQ) for USB OTG FS, and SDIO clocks" if CUSTOM_PLL_PARAMS
    default 5 if CPU_FAM_F2
    default 7 if CPU_FAM_F4 && CLOCK_MAX_84MHZ
    default 4 if CPU_FAM_F4 && CLOCK_MAX_100MHZ
    default 7 if CPU_FAM_F4 && CLOCK_MAX_180MHZ && (MODULE_PERIPH_USBDEV_CLK || USEMODULE_PERIPH_USBDEV_CLK) && !HAVE_CLOCK_ALT_48MHZ
    default 9 if CPU_FAM_F7
    default 13 if CPU_FAM_MP1
    default 8
    range 2 15

endif # CPU_FAM_F2 || CPU_FAM_F4 || CPU_FAM_F7 || CPU_FAM_MP1