/* * Copyright (C) 2016 OTA keys * * This file is subject to the terms and conditions of the GNU Lesser * General Public License v2.1. See the file LICENSE in the top level * directory for more details. */ /** * @ingroup boards_nucleo32-f042 * @{ * * @file * @brief Peripheral MCU configuration for the nucleo32-f042 board * * @author Vincent Dupont */ #ifndef PERIPH_CONF_H #define PERIPH_CONF_H #include "periph_cpu.h" #ifdef __cplusplus extern "C" { #endif /** * @name Clock system configuration * @{ */ #define CLOCK_HSI (8000000U) /* internal oscillator */ #define CLOCK_CORECLOCK (48000000U) /* desired core clock frequency */ /* the actual PLL values are automatically generated */ #define CLOCK_PLL_MUL (CLOCK_CORECLOCK / CLOCK_HSI) /* bus clocks for simplified peripheral initialization, UPDATE MANUALLY! */ #define CLOCK_AHB (CLOCK_CORECLOCK / 1) #define CLOCK_APB1 (CLOCK_CORECLOCK / 1) #define CLOCK_APB2 (CLOCK_CORECLOCK / 1) /** @} */ /** * @name Timer configuration * @{ */ static const timer_conf_t timer_config[] = { { .dev = TIM2, .max = 0xffffffff, .rcc_mask = RCC_APB1ENR_TIM2EN, .bus = APB1, .irqn = TIM2_IRQn } }; #define TIMER_0_ISR isr_tim2 #define TIMER_NUMOF (sizeof(timer_config) / sizeof(timer_config[0])) /** @} */ /** * @name UART configuration * @{ */ static const uart_conf_t uart_config[] = { { .dev = USART2, .rcc_mask = RCC_APB1ENR_USART2EN, .rx_pin = GPIO_PIN(PORT_A, 15), .tx_pin = GPIO_PIN(PORT_A, 2), .rx_af = GPIO_AF1, .tx_af = GPIO_AF1, .bus = APB1, .irqn = USART2_IRQn }, { .dev = USART1, .rcc_mask = RCC_APB2ENR_USART1EN, .rx_pin = GPIO_PIN(PORT_A, 10), .tx_pin = GPIO_PIN(PORT_A, 9), .rx_af = GPIO_AF1, .tx_af = GPIO_AF1, .bus = APB2, .irqn = USART1_IRQn } }; #define UART_0_ISR (isr_usart2) #define UART_1_ISR (isr_usart1) #define UART_NUMOF (sizeof(uart_config) / sizeof(uart_config[0])) /** @} */ /** * @name PWM configuration * @{ */ static const pwm_conf_t pwm_config[] = { { .dev = TIM1, .rcc_mask = RCC_APB2ENR_TIM1EN, .chan = { { .pin = GPIO_PIN(PORT_A, 8) /* D9 */, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 } }, .af = GPIO_AF2, .bus = APB2 }, { .dev = TIM14, .rcc_mask = RCC_APB1ENR_TIM14EN, .chan = { { .pin = GPIO_PIN(PORT_B, 1) /* D6 */, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 } }, .af = GPIO_AF0, .bus = APB1 }, { .dev = TIM3, .rcc_mask = RCC_APB1ENR_TIM3EN, .chan = { { .pin = GPIO_PIN(PORT_B, 0) /* D3 */, .cc_chan = 2 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }, { .pin = GPIO_UNDEF, .cc_chan = 0 }}, .af = GPIO_AF1, .bus = APB1 } }; #define PWM_NUMOF (sizeof(pwm_config) / sizeof(pwm_config[0])) /** @} */ /** * @name RTC configuration * @{ */ /** * Nucleo-f042 does not have any LSE, current RTC driver does not support LSI as * clock source, so disabling RTC. */ #define RTC_NUMOF (0U) /** @} */ /** * @name ADC configuration * @{ */ #define ADC_CONFIG { \ { GPIO_PIN(PORT_A, 0), 0 }, \ { GPIO_PIN(PORT_A, 1), 1 }, \ { GPIO_PIN(PORT_A, 3), 3 }, \ { GPIO_PIN(PORT_A, 4), 4 }, \ { GPIO_PIN(PORT_A, 7), 7 } \ } #define ADC_NUMOF (5) /** @} */ /** * @name DAC configuration * @{ */ #define DAC_NUMOF (0) /** @} */ #ifdef __cplusplus } #endif #endif /* PERIPH_CONF_H */ /** @} */