# Copyright (c) 2020 Inria
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#

config CLOCK_HAS_NO_MCO_PRE
    bool
    help
        Indicates that the CPU has no MCO prescaler


choice
bool "Clock source selection"
default USE_CLOCK_PLL

config USE_CLOCK_PLL
    bool "PLL"

config USE_CLOCK_HSE
    bool "Direct High frequency external oscillator (HSE)"
    depends on BOARD_HAS_HSE

config USE_CLOCK_HSI
    bool "Direct High frequency internal oscillator (HSI16)"

endchoice

config CLOCK_HSE
    int
    depends on BOARD_HAS_HSE
    default 24000000 if CPU_FAM_G0 || CPU_FAM_G4 || CPU_FAM_L0 || CPU_FAM_L1 || CPU_FAM_MP1
    default 8000000

config CUSTOM_PLL_PARAMS
    bool "Configure PLL parameters"
    depends on USE_CLOCK_PLL

choice
bool "APB1 prescaler (division factor of HCLK to produce PCLK1)"
default CLOCK_APB1_DIV_4 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL
default CLOCK_APB1_DIV_2 if CPU_FAM_F1 || CPU_FAM_F3 || CPU_FAM_F4 || CPU_FAM_MP1
default CLOCK_APB1_DIV_1

config CLOCK_APB1_DIV_1
    bool "Divide HCLK by 1"

config CLOCK_APB1_DIV_2
    bool "Divide HCLK by 2"

config CLOCK_APB1_DIV_4
    bool "Divide HCLK by 4"

config CLOCK_APB1_DIV_8
    bool "Divide HCLK by 8"

config CLOCK_APB1_DIV_16
    bool "Divide HCLK by 16"

endchoice

config CLOCK_APB1_DIV
    int
    default 1 if CLOCK_APB1_DIV_1
    default 2 if CLOCK_APB1_DIV_2
    default 4 if CLOCK_APB1_DIV_4
    default 8 if CLOCK_APB1_DIV_8
    default 16 if CLOCK_APB1_DIV_16

choice
bool "APB2 prescaler (division factor of HCLK to produce PCLK2)"
depends on !CPU_FAM_G0 && !CPU_FAM_F0
default CLOCK_APB2_DIV_2 if CPU_FAM_F2 || (CPU_FAM_F4 && CLOCK_MAX_180MHZ) || CPU_FAM_F7 || CPU_FAM_L4 || CPU_FAM_L5 || CPU_FAM_U5 || CPU_FAM_WB || CPU_FAM_WL || CPU_FAM_MP1
default CLOCK_APB2_DIV_1

config CLOCK_APB2_DIV_1
    bool "Divide HCLK by 1"

config CLOCK_APB2_DIV_2
    bool "Divide HCLK by 2"

config CLOCK_APB2_DIV_4
    bool "Divide HCLK by 4"

config CLOCK_APB2_DIV_8
    bool "Divide HCLK by 8"

config CLOCK_APB2_DIV_16
    bool "Divide HCLK by 16"

endchoice

config CLOCK_APB2_DIV
    int
    default 1 if CLOCK_APB2_DIV_1
    default 2 if CLOCK_APB2_DIV_2
    default 4 if CLOCK_APB2_DIV_4
    default 8 if CLOCK_APB2_DIV_8
    default 16 if CLOCK_APB2_DIV_16