# Copyright (c) 2021 Inria
# Copyright (c) 2021 Freie Universitaet Berlin
#
# This file is subject to the terms and conditions of the GNU Lesser
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
#

config CPU_FAM_WL
    bool
    select CPU_STM32
    select CPU_CORE_CORTEX_M4
    select HAS_CPU_STM32WL
    select HAS_PERIPH_FLASHPAGE
    select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
    select HAS_PERIPH_FLASHPAGE_PAGEWISE
    select HAS_PERIPH_GPIO_LL
    select HAS_PERIPH_GPIO_LL_IRQ
    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
    select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_LOW
    select HAS_PERIPH_RTC_MEM
    select HAS_PERIPH_VBAT
    select HAS_PERIPH_WDT
    select HAS_BOOTLOADER_STM32

config CPU_FAM
    default "wl" if CPU_FAM_WL

config HAS_CPU_STM32WL
    bool
    help
        Indicates that the cpu being used belongs to the 'stm32wl' family.

config STM32_WL55JC_SUBGHZ_DEBUG
     bool "STM32WL->Enable Hardware Debugging"
     help
        Enable Hardware debug pins. This would affect onboard peripherals such as SPI
        as the pins are multiplexed. For more information check Alternate Functions
        column in Table 19 : STM32WL55/54xx pin definition in STM32WL55/54xx
        datasheet.