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Commit Graph

7 Commits

Author SHA1 Message Date
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
32399901f0
fe310: Unify linker scripts
Similar to the cortex-m common linker scripts, the RISC-V linker scripts
can be unified easily, requiring only the memory addresses and lengths.
This simplifies adding new RISC-V CPU's later
2020-09-01 14:39:55 +02:00
3869397ed3
cpu/fe310: move dependencies to Makefile.dep 2020-01-28 13:20:52 +01:00
smlng
2de4b3011b periph_common: add as dependency to periph drivers
Rational: the periph_common module is required by (most) other periph drivers
and also during startup of the CPU/MCU to run periph_init. The latter is only
required if other periph drivers are used, hence periph_common should be a
depency of periph_* modules and *not* of the CPU/MCU. This PR fixes that
by making periph_common a depency of periph_* and removing the explicit
include in the CPU/MCU implementation.
2019-06-03 13:44:10 +02:00
Marian Buschsieweke
08fba76fa6
cpu/fe310: Add call to periph_init()
Until now fe310's cpu_init() was missing a call to periph_init().
This commit adds this call.
2019-01-19 13:00:36 +01:00
kenrabold
db4d67c4fd make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit

build: fixed missing syscall and cpuid failures

Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph

build: fixed whitespace error

build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY

doc: fixed doxygen warnings

Addressed Doxygen warnings in source file comments

doc: more doxygen fixes

doc: even more doxygen fixes

doc: more changes

build: fix pedantic and rdci_simple build failures

make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00