10 Commits

Author	SHA1	Message	Date
Gunar Schorcht	2ae7566a89	cpu/riscv_common: rename cpu.h to cpu_common.h ... To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.	2023-04-18 06:20:14 +02:00
Koen Zandberg	2692957c0e	riscv_common: Refactor common fe310 code to riscv_common	2021-02-05 09:32:19 +01:00
Alexandre Abadie	ace160a2a3	boards/hifive1: use MHZ utility macro for clock frequency	2020-09-09 14:14:39 +02:00
Koen Zandberg	498646aa17	fe310: Remove vendor plic driver	2020-08-31 16:26:43 +02:00
Alexandre Abadie	fc911bf6c5	cpu/fe310: rework clock initialization	2020-01-10 16:41:33 +01:00
Alexandre Abadie	97e1c7ba7e	cpu/fe310: reorganize files and includes	2020-01-10 16:41:33 +01:00
Alexandre Abadie	e5c64c739a	cpu/fe310: rework uart driver implem/config	2019-12-20 15:22:09 +01:00
Alexandre Abadie	b49cca2d0c	cpu/fe310: include thread.h in cpu.h ... This ensures the ARRAY_SIZE macro is implicitly available	2019-12-13 16:25:11 +01:00
kenrabold	db4d67c4fd	make: add hifive1 to BOARD_INSUFFICIENT_MEMORY ... Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit build: fixed missing syscall and cpuid failures Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph build: fixed whitespace error build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY doc: fixed doxygen warnings Addressed Doxygen warnings in source file comments doc: more doxygen fixes doc: even more doxygen fixes doc: more changes build: fix pedantic and rdci_simple build failures make: exclude lua	2018-05-29 16:27:53 -07:00
kenrabold	7d1d5e77d8	cpu/fe310: add RISC-V cpu FE310 ... New CPU FE310 from SiFive based on RISC-V architecture build: add makefile for RISC-V builds Makefile for builds using RISC-V tools	2018-05-29 15:21:45 -07:00