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Commit Graph

10 Commits

Author SHA1 Message Date
Gunar Schorcht
b4fafef6e7 cpu/esp_common: replace FLASH_MODE_* by CONFIG_*FLASHMODE_* defines
The former FLASH_MODE_{DOUT,DIO,QOUT,QIO} defines are replaced by the corresponding CONFIG_FLASHMODE_{DOUT,DIO,QOUT,QIO} and CONFIG_ESPTOOLPY_FLASHMODE_{DOUT,DIO,QOUT,QIO} as used by the ESP-IDF. This is also needed for the migration of defining flash mode in Kconfig.
2022-08-01 15:17:33 +02:00
iosabi
52107b2416 esp8266: Support UART1 and other UART0 pins.
The esp8266 CPU has actually two hardware UART peripherals. UART0 is
used by the boot ROM for flashing and serial output during boot,
typically at a baudrate of 74880 bps until the bootloader or application
sets the more standard 115200 baudrate. This UART0 device has two
possible pins for TXD, GPIO1 and GPIO2, which are both set to TXD by the
boot ROM. esp8266 modules will typically have GPIO1 labeled as the TX
pin, but it is possible to use GPIO2 for that purpose even while
flashing the device with esptool.py.

The second device, UART1, also has two options for TXD, GPIO2 and GPIO7,
and only one option for RXD, GPIO8. However, GPIO7 and GPIO8 are used
by the flash internally so those options are not very useful unless
maybe while running from IRAM with the flash disabled, for example for
a debugger over UART1.

This patch allows boards to override UART{0,1}_{R,T}XD in their
periph_conf.h to configure the uart selection. Defining UART1_TX will
make the UART_DEV(1) device available.

Tested with:

```CFLAGS='-DUART1_TXD=GPIO2' make -C tests/periph_uart BOARD=esp8266-esp-12x flash term```

* Connected one USB-UART to the standard GPIO1 and GPIO3 for flashing
  and console. After flashing we see the manual test output at 115200
  bps

* Connected a second USB-UART with RX to GPIO2 running at 74880.

Then run on the first console:
```
> init 1 74880
> send 1 hello
```

The word "hello" appears on the second UART connection.

Note that GPIO2 is used during boot for UART0's TX until the application
or bootloader set it to a regular GPIO, so some boot ROM messages at
74880 bps are visible. After running `init 1 74880` it is set to UART1's
TX.
2021-05-02 12:27:27 +00:00
Bas Stottelaar
bd34cf8fc0 cpu/*: reorder ENABLE_DEBUG after last include 2020-10-23 00:45:55 +02:00
Gunar Schorcht
ddc91df4ca cpu/esp8266: changes for RTOS SDK 2019-11-14 13:58:22 +01:00
Peter Kietzmann
b2c791c6cb
Merge pull request #10135 from miri64/cpu/enh/periph-gpio-irq-closing-endif
cpu, periph_gpio: mark closing #endif for MODULE_PERIPH_GPIO_IRQ
2018-10-15 13:41:02 +02:00
Kevin "Bear Puncher" Weiss
9a75ee0d47
Merge pull request #10127 from gschorcht/esp8266_i2c_fix
cpu/esp8266: improvements of I2C implementation
2018-10-10 17:13:34 +02:00
Gunar Schorcht
4fcfb7ca06 cpu/esp8266: i2c improvements
The commit
- improves the timing of the SDA and SCL signals that fixes communication problems with some slaves (#10115),
- introduces the internal function _i2c_clear which clears the bus when SDA line is locked at LOW, and
- renames internal _i2c_*_sda and _i2c_*_scl functions to function names that are more clear, e.g., _i2c_clear_sda to _i2c_sda_low.
2018-10-10 12:17:20 +02:00
Martine Lenders
ce12d4cefb esp8266: mark closing #endif for MODULE_PERIPH_GPIO_IRQ 2018-10-09 15:11:00 +02:00
Hauke Petersen
8ff5c91d9f cpu/esp8266/gpio: use gpio_irq feature 2018-09-21 08:17:52 +02:00
Schorcht
e4ca897661 cpu: add esp8266 2018-09-05 02:39:50 +02:00