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Commit Graph

5 Commits

Author SHA1 Message Date
f2787448e1 cpu/riscv_common: Move MCAUSE defines to riscv_common 2021-08-24 14:30:23 +02:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00
1d999a1335
fe310: Make header guard unique for plic vendor header
Otherwise it conflicts with the other plic.h header
2020-08-31 16:26:43 +02:00
kenrabold
97d1dc0821 cpu/fe310: Add support for FE310_G002
Added support for FE310_G002 CPU variant that is on new HiFive1B board
2019-07-19 13:25:17 -07:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00