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Commit Graph

37 Commits

Author SHA1 Message Date
Ollrogge
6a8bbe0240 Revert "cpu/cortexm_common: extend flashpage API"
This reverts commit d38f6c68b5.
2024-04-04 17:57:40 +02:00
Benjamin Valentin
308374fc29 cpu/cortexm_common: allow to define AUX slot on flash 2024-02-28 11:49:05 +01:00
Keith Packard
fb01e6a3fb cpu: Add TLS symbols for newer picolibc to linker scripts
Newer picolibc versions require some additional symbols defined in the
linker script to correctly manage alignment constraints on thread
local storage.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-03-02 22:55:22 -08:00
Ollrogge
5587f5d88f cpu/cortexm_common: add flash_writable section to linker script 2022-03-07 11:23:44 +01:00
Ollrogge
d38f6c68b5 cpu/cortexm_common: extend flashpage API 2021-10-19 22:33:15 +02:00
8f10f22b1f cpu/cortexm: ldscripts: bkup-ram -> bkup_ram
Fixes this error with binutils 2.37:

```
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: warning: memory region `bkup' not declared
/usr/lib/gcc/arm-none-eabi/11.2.0/../../../../arm-none-eabi/bin/ld:cortexm_base.ld:217: syntax error
```
2021-08-18 10:29:38 +02:00
858b5ca6ed xfa: remove obsolete empty xfa.ld 2021-02-18 10:46:08 +01:00
d8d34e033c cpu/cortexm_common: add XFA handling to linkerscript
The global core/ldscripts/xfa.ld doesn't match our cortexm_base.ld.
This commit directly adds the two XFA lines to cortexm_base.ld.
In addition to that, a dummy (empty) xfa.ld is added, which the linker will pick
instead of core/ldscripts/xfa.ld, effectingly not using it.
2021-02-18 10:46:08 +01:00
Keith Packard
531050ada2 picolibc: Enable TLS support [v4]
Allocate and initialize a thread-local block for each thread at the
top of the stack.

Set the tls base when switching to a new thread.

Add tdata/tbss linker instructions to cortex_m and risc-v scripts.

Signed-off-by: Keith Packard <keithp@keithp.com>

---

v2:
	Squash fixes

v3:
	Replace tabs with spaces

v4:
	Add tbss to fe310 linker script
2020-08-24 08:26:16 -07:00
Benjamin Valentin
cfd0ef415e cpu/sam0_common: hook up low power RAM as extra heap
This enables unused low-lower RAM on saml21/samd5x to be used for
heap memory.
2020-02-20 17:11:25 +01:00
Benjamin Valentin
2c09d9bd5b cpu/cortexm_common: Make Low-Power SRAM available to programs
Many MCUs contain some Backup or Low Power SRAM that is retained'even
in the deepest sleep modes.

In such sleep modes the MCU is essentually turned off with only the RTC
still running.
It can be woken by a GPIO or a RTC alarm. When this happens, a reset is
triggered and the normal startup routine is invoked.

This adds bss & data section for this memory in the linker script.
This allows for structures to be placed in it e.g.:

e.g.:

    static uint8_t persistent_buffer[64] __attribute__((section(".backup.bss")));
    static uint32_t persistent_counter __attribute__((section(".backup.data"))) = 1234;
2019-10-01 18:39:40 +02:00
Gaëtan Harter
bbb6dec054
Merge pull request #11630 from fjmolinas/pr_kinetis_ld
kinetis/ldscript: handle _rom_offset
2019-06-05 16:12:25 +02:00
francisco
43182bd8f7 cortexm_common/ldscript: use cortexm_rom_offset.ld 2019-06-04 18:05:35 +02:00
francisco
1e5a485539 cortexm_common/ldscript: add common script for rom_offset calculation 2019-06-04 18:05:35 +02:00
Benjamin Valentin
1c3f96495d ldscripts: move .noinit section behind .bss section
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
2019-05-16 23:11:45 +02:00
Benjamin Valentin
29bf6c712b cortexm_common: add .noinit section
Make it possible to specify a section of RAM that is not touched by
the init routing so data can be kept across resets.

This should behave the same as on atmega & lpc2387.
2019-05-14 12:10:27 +02:00
3163b8d6e2
nrf52: use cortexm.ld script when applicable
The common linker script is not used when the nordic_softdevice_ble is
included
2019-03-13 11:57:44 +01:00
Gaëtan Harter
7dad2e7096
cortexm_common/ldscript: allow defining FW_ROM_SIZE
Allow defining a specific rom length to use for linking the firmware,
_fw_rom_length, instead of the default configuration to use the whole rom from
_rom_offset to the end.

 * Add cortexm_common/Makefile.include FW_ROM_SIZE configuration
 * Add an assertion that _fw_rom_length still respects _rom_length
2018-08-11 11:34:01 +02:00
Gaëtan Harter
83a617261a
cortexm_common/ldscript: add _fw_rom_length variable
It will help testing if it is taken into account and for defining for outside
after.
2018-08-11 11:33:47 +02:00
Gaëtan Harter
d9db258411
cortexm_common/ldscript: re-use _rom_offset variable name
Inspired by kaspar030 version to removing the new _boot_offset variable.

cbf324a66d/cpu/cortexm_common/ldscripts/cortexm.ld
2018-08-11 11:33:39 +02:00
PeterKietzmann
20397c5b15 cortexm_common: add SRAM based PRNG seeder 2018-07-04 17:55:16 +02:00
Joakim Nohlgård
4532c348b4 cortexm_common: Adjust ldscript memory segment attributes 2018-05-09 06:44:12 +02:00
Joakim Nohlgård
b8d6bcdb07 cortexm_common: specify load segment instead of load address for .data 2018-05-09 00:41:27 +02:00
kYc0o
d25fd647e7 cpu/cortexm_common/ldscripts: add common linker script for cortexm family 2017-11-07 15:05:43 +01:00
Joakim Nohlgård
2f55fdcec4 cortexm_common: Correct offset for hardfault stack
The required space for the hardfault handler is defined by
HARDFAULT_HANDLER_REQUIRED_STACK_SPACE, which is given in bytes,
this length is added to &_sram to find a lower limit on the amount of
stack space that the hard fault handler can work with. The _sram
variable, was mistakenly defined as a uint32_t, which makes &_sram into
a uint32_t*, which through pointer addition, made the required space 4
times as big as it was supposed to. By changing the type of _sram to
uint8_t, the required stack space is correctly computed.

The symptom was that the hardfault handler always reported that the
stack pointer had been corrupted and it was impossible to get any useful
information from the crash text.
2017-10-30 07:08:33 +01:00
167bd30453 all: fix my email address 2017-10-20 15:02:41 +02:00
Hauke Petersen
1a20ef8223 cpu: unified cortex-m base interrupt vector 2017-09-04 15:13:32 +02:00
kYc0o
1a52c80bf4 cpu/cortexm_common/ldscripts: add multislot variables 2017-07-17 14:48:28 +02:00
Vincent Dupont
f656a31e58 cpu/cortexm_common: use linker variable to initialize SCB->VTOR 2017-03-17 18:07:22 +01:00
Oleg Hahm
c5abb08316 Merge pull request #4058 from daniel-k/pr/gdb_threads_openocd
cortex_m: Add debug symbols for OpenOCD/GDB thread support
2017-01-25 17:49:42 +01:00
daniel-k
9d403d95ce cortex_m: Add debug symbols for OpenOCD/GDB thread support 2017-01-16 20:50:35 +01:00
Antoine Faure
31e675b359 cpu: cortex_common: Add entry point to tell gdb where to start 2016-07-23 13:27:47 +02:00
Ian Martin
87e06756a5 cortexm_common: move the stack to the bottom of RAM 2016-05-19 15:55:36 -04:00
Hauke Petersen
cf11b073d6 cpu/cortexm_common: define ISR stacksize in cpu.h 2015-11-19 11:55:35 +01:00
daniel-k
7a86344c4d cpu/cortexm_common: gather addition information on hardfault 2015-08-19 14:24:54 +02:00
Hauke Petersen
19ef9dbe4e cpu/cortexm: raised ISR stack size to safer value
256 Byte were not enough for some boards (not sure why, yet).
So go back to 512 byte as a save (and known working value).
2015-05-31 12:00:17 +02:00
Hauke Petersen
8752894cc9 cpu/cortexm: added base linkerscript 2015-05-30 13:43:19 +02:00