CPU_HAS_SRAM_BITBAND can be used to check whether bit-banding is supported for
all of SRAM. With partially supported bit-banding, this feature is more of a
foot gun that a valuable tool.
It is often desiderable to sync on multiple threads, e.g. there can be a controller
thread that waits for `n` worker threads to finish their job.
An inverse semaphore provides an easy primitive to implement this pattern.
After being initialized with a value `n` (in counter mode), a call to `sema_inv_wait()`
will block until each of the `n` threads has called `sema_inv_post()` exactly once.
There are situations where workers might post an event more than once
(unless additional state is introduced).
For this case, the alternative mask mode is provided.
Here the inverse semaphore is initialized with a bit mask, each worker can clear one
or multiple bits with `sema_inv_post_mask()`. A worker can clear it's bit multiple times.
Previously a value of 0 was used for the RSSI to signal that this value is not
present in `gnrc_netif_hdr_t`. However, an RSSI of 0 dBm is legal and even very
plausible data.
This commit defines `GNRC_NETIF_HDR_NO_RSSI` as `INT16_MIN`, which is below the
noise floor in the vacuum of outer space and hence impossible to receive.
For consistency, also GNRC_NETIF_HDR_NO_LQI is defined.
The logic used to check whether the RX timestamp was provided in the GNRC
implementation of `sock_ip_recv_buf_aux()` is incorrect: It still uses in-band
signalling via a timestamp of zero, but a dedicated flag was added to allow for
timestamps of zero.
Additionally, it is not necessary to check if a bit is set only to clear it -
clearing it unconditionally is faster and smaller.
When dumping memory the printed addresses always start with `00000000`.
This can be very confusing and lead to errors.
Allow the user to specify a starting address of the printed memory that
will be used instead.
By introducing a wrapper function, existing users are unaffected.
