Francisco Molina
4d398ab09e
cpu/stm32f1: add unified rtt configuration
2020-04-24 08:57:04 +02:00
Francois Berder
4a31f94cfc
many typo fixes
...
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
2019-11-23 22:39:07 +01:00
58e172e4df
cpu/stm32_common: always enable PWR module
2018-03-06 14:55:32 +01:00
Hauke Petersen
87200c4803
cpu/stm32: removed file guards from periph drivers
2017-11-09 16:27:24 +01:00
Oleg Hahm
650d297890
stm32f1: rtt: declare functions static
2017-07-28 11:24:03 +02:00
smlng
692cf96297
doc: fix doxygen grouping of cpu periph drivers
2017-06-26 14:42:11 +02:00
Hauke Petersen
3a00fe8e49
cpus: make use of cortexm_isr_end()
2016-12-21 11:28:46 +01:00
Pieter Willemsen
a0835ccb1d
stm32: use periph_clk_en/dis functions for clock changes
2016-12-16 15:01:56 +01:00
Joakim Nohlgård
96a7583c2a
cpu/stm32f1: Use {} notation for empty while loops
2016-03-03 16:31:25 +01:00
Joakim Gebart
13832d8e62
everything: Remove filename from @file Doxygen command
2015-05-22 07:34:41 +02:00
Hauke Petersen
65520865b1
cpu/stm32f1: adjusted to RTT interface changes
2014-11-07 12:29:31 +01:00
Hauke Petersen
e7fbaf3815
cpu: removed NAKED attribute from ISRs
...
- removed the __attribute__((naked)) from ISRs
- removed ISR_ENTER() and ISR_EXIT() macros
Rationale: Cortex-Mx MCUs save registers R0-R4 automatically
on calling ISRs. The naked attribute tells the compiler not
to save any other registers. This is fine, as long as the
code in the ISR is not nested. If nested, it will use also
R4 and R5, which will then lead to currupted registers on
exit of the ISR. Removing the naked will fix this.
2014-10-30 19:33:32 +01:00
Thomas Eichinger
a16d326bf0
stm32f1: implement RTT driver
2014-10-09 11:13:06 +02:00
