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Commit Graph

6 Commits

Author SHA1 Message Date
32399901f0
fe310: Unify linker scripts
Similar to the cortex-m common linker scripts, the RISC-V linker scripts
can be unified easily, requiring only the memory addresses and lengths.
This simplifies adding new RISC-V CPU's later
2020-09-01 14:39:55 +02:00
Keith Packard
531050ada2 picolibc: Enable TLS support [v4]
Allocate and initialize a thread-local block for each thread at the
top of the stack.

Set the tls base when switching to a new thread.

Add tdata/tbss linker instructions to cortex_m and risc-v scripts.

Signed-off-by: Keith Packard <keithp@keithp.com>

---

v2:
	Squash fixes

v3:
	Replace tabs with spaces

v4:
	Add tbss to fe310 linker script
2020-08-24 08:26:16 -07:00
Benjamin Valentin
0ddca68de9 cpu/fe310: use common names for heap markers
Other archs use `_sheap` and `_eheap` to mark the start and end of
the heap.

fe310 uses `_heap_start` and `_heap_end`, so platform independent
code that wants to make use of this will needlessly fail.

For compatibility with common code, name them the same on fe310.
2020-07-07 17:25:00 +02:00
kenrabold
1d6e37a7f7 cpu/fe310: interrupt handling cleanup
Cleanup of FE310 interrupt handler code
Optimization of intr context frame
Reduce size of intr stack
Added unhandled trap output
Fix PR #12237
2019-09-27 13:32:43 -07:00
kenrabold
97d1dc0821 cpu/fe310: Add support for FE310_G002
Added support for FE310_G002 CPU variant that is on new HiFive1B board
2019-07-19 13:25:17 -07:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00