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2 Commits

Author SHA1 Message Date
1bc82c2378 cpu/fe310: periph/timer: reset counter in timer_init() 2019-02-21 11:34:59 +01:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00