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Commit Graph

10 Commits

Author SHA1 Message Date
Joakim Gebart
afc1dd3a6d cortex-m4: Add atomic_cas implementation 2015-05-07 18:52:13 +02:00
Joakim Gebart
215ccc1213 core: Introduce atomic counters
- Move generic implementation of atomic_set_return to core/atomic.c
 - Generic implementation of atomic compare and swap in core/atomic.c
 - atomic_cas is used to implement atomic counters in core/include/atomic.h
 - atomic_int_t is an atomic integer type
 - ATOMIC_INIT can be used as an initializer for atomic_int_t
 - ATOMIC_VALUE gets a reference to the value of an atomic integer
2015-05-07 18:52:13 +02:00
Joakim Gebart
53b29f40e7 cortex-m4: Add extern "C" to core_cmInstr.h
Signed-off-by: Joakim Gebart <joakim.gebart@eistec.se>
2015-01-29 10:18:28 +01:00
Joakim Gebart
0d8aaf86a8 cortex-m4: Add extern "C" to core_cmFunc.h
Signed-off-by: Joakim Gebart <joakim.gebart@eistec.se>
2015-01-29 10:18:28 +01:00
Joakim Gebart
fe43bb2b7a cortex-m4: Update to CMSIS HAL 4.0
Signed-off-by: Joakim Gebart <joakim.gebart@eistec.se>
2015-01-29 09:38:31 +01:00
BytesGalore
a4d2ee307c cpu: added extern "C" to headers 2014-11-24 19:10:15 +01:00
Hauke Petersen
e7fbaf3815 cpu: removed NAKED attribute from ISRs
- removed the __attribute__((naked)) from ISRs
- removed ISR_ENTER() and ISR_EXIT() macros

Rationale: Cortex-Mx MCUs save registers R0-R4 automatically
on calling ISRs. The naked attribute tells the compiler not
to save any other registers. This is fine, as long as the
code in the ISR is not nested. If nested, it will use also
R4 and R5, which will then lead to currupted registers on
exit of the ISR. Removing the naked will fix this.
2014-10-30 19:33:32 +01:00
Hinnerk van Bruinehsen
d5fe9de5e5 cpu: change __ASM to asm (cppcheck uninitvar error) 2014-09-17 00:20:20 +02:00
Ludwig Ortmann
651cb6ca9f doc: tailor CMSIS doxygen for license checker
Remove '@par' within the license header to allow the existing regular
expression to match it.
2014-09-15 08:27:59 +02:00
Hauke Petersen
29e70c14d6 cpu: Initial import of cortex-m4_common 2014-07-16 17:20:50 +02:00