The Watchdog on the CC2538 only supports 4 intervals (2ms, 16ms, 250ms & 1s).
Since the watchdog timer API specifies a `max_time`, the interval equal or
below that time is selected.
E.g. for `max_time=125ms` the 16ms interval would be selected.
This is outside the tolerance of the `tests/periph_wdt` test.
Co-authored-by: Thomas Geithner <thomas.geithner@dai-labor.de>
The interval load value was only set to 0xffff regardless of the counter
mode used which mad the 32bit timer apparently stop after 0xffff (it
would never reach values >0xffff).
When a GPTM is configured to one of the 32-bit modes, TAILR appears as a
32-bit register (the upper 16-bits correspond to the contents of the
GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the
state of TBILR.
Thsi commit set the correct value for TAILR depending on the configured
timer mode.
Previously the setting the alarm would overwrite the overflow callback
and vice versa.
Since we can only set one alarm in hardware, always set the alarm to the
closest event of the two.
If only one it is set in state (one GPIO pin caused an interrupt),
don't loop over all 8 bits.
Use clz to get the position of the first interrupt bit and clear it,
looping only as many times as there are actual interrupts.
cc2538 implements 4 sleep modes.
In the lightest mode (3) any interrupt source can wake up the CPU.
In mode 2, only RTT, GPIO or USB may wake the CPU.
In mode 1 only RTT and GPIO can wake the CPU.
In mode 0 only GPIO can wake the CPU.
In mode 0 and 1 the lower 16k RAM are lost. This is a problem since those
are usually used by RIOT.
The linkerscripts in cc2538/ldscripts take different approaches towards that.
Some only use the upper 16k and leave the other half to be managed by the
application.
`cc2538sf53.ld` which is used by `openmote-b` uses the entire RAM starting
at the lower half, so it will not be able to wake up from those modes.
A quick fix to test those modes with `tests/periph_pm` would be
--- a/cpu/cc2538/ldscripts/cc2538sf53.ld
+++ b/cpu/cc2538/ldscripts/cc2538sf53.ld
@@ -21,7 +21,7 @@ MEMORY
{
rom (rx) : ORIGIN = 0x00200000, LENGTH = 512K - 44
cca : ORIGIN = 0x0027ffd4, LENGTH = 44
- ram (w!rx) : ORIGIN = 0x20000000, LENGTH = 32K
+ ram (w!rx) : ORIGIN = 0x20004000, LENGTH = 16K
}
We have to read the DR for every byte that we write.
Just reading DR while SPI is busy in a loop can lead to bytes being
left in the fifo, corrupting subsequent reads.
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Adapt the periph ADC implementation to use vendor defines where
ever possible. Remove duplicate or obsolete defines and adapt
board configuration as required.
Rework SPI periph driver to use proper RIOT GPIO API functions.
Also cleanup header files by using vendor defines and remove
obsolete code. Further, adapt board config accordingly.
Remove unused or obsolete defines in headers, due to usage of
vendor headers. Also remove register bit definition in timer
struct because they where not used in the implementation.
Changed the style of the UART configuration for different boards,
from a define based configuration to one based on an array of
structs, one struct for each UART, with the format of the struct defined
in cc2538/include/periph_cpu.h.
- Defined the fields of the struct in periph_cpu.h
- Removed the compilation includes that were in uart.c for each UART
- Implemented a generic ISR subroutine for clarity
- combined uart_base and uart_init in uart.c
- used bitmask for the interrupt setup
- took the uart Rx, Tx, and IRQ numbers out of the config
(as this has to match the .dev field). Replaced with
macros from the uart number
- took out some unused code
- implemented power on/off commands
- removed reset function - now bytes are just discarded on error
- Rx now not initialised if Rx callback = NULL, as per
drivers/periph/uart.h
- device is now enabled after callbacks are set, not before
- asserts raised if rts and cts are enabled for UART0
- BIT macro removed
