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Commit Graph

5 Commits

Author SHA1 Message Date
Keith Packard
a0d3436486 cpu/fe310: Add PICOLIBC support [v3]
Disable the newlib-nano stubs code when picolibc is in use

Signed-off-by: Keith Packard <keithp@keithp.com>

---
v2:
	Squash fixes in
v3:
	call stdio_init in _PICOLIBC_ mode to initialize uart
v3:
	Remove call to stdio_init from nanostubs_init, always
	call from cpu_init.
2020-08-24 08:24:54 -07:00
Benjamin Valentin
0ddca68de9 cpu/fe310: use common names for heap markers
Other archs use `_sheap` and `_eheap` to mark the start and end of
the heap.

fe310 uses `_heap_start` and `_heap_end`, so platform independent
code that wants to make use of this will needlessly fail.

For compatibility with common code, name them the same on fe310.
2020-07-07 17:25:00 +02:00
Hauke Petersen
c2184f3454 boards/cpu/drivers/sys: use generic stdio_ if 2018-08-22 10:54:25 +02:00
kenrabold
db4d67c4fd make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit

build: fixed missing syscall and cpuid failures

Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph

build: fixed whitespace error

build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY

doc: fixed doxygen warnings

Addressed Doxygen warnings in source file comments

doc: more doxygen fixes

doc: even more doxygen fixes

doc: more changes

build: fix pedantic and rdci_simple build failures

make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8 cpu/fe310: add RISC-V cpu FE310
New CPU FE310 from SiFive based on RISC-V architecture

build: add makefile for RISC-V builds

Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00